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Commit 00b06296 authored by Vathsala Nagaraju's avatar Vathsala Nagaraju Committed by Dhinakaran Pandiyan
Browse files

drm/i915/psr: Add psr1 live status 



Prints live state of psr1.Extending the existing
PSR2 live state function to cover psr1.

Tested on KBL with psr2 and psr1 panel.

v2: rebase
v3: DK
    Rename psr2_live_status to psr_source_status.
v4: DK
    Move EDP_PSR_STATUS_STATE_SHIFT below EDP_PSR_STATUS_STATE_MASK.
    Pass seq to psr_source_status, handle source status prints in
    psr_source_status.
v5: Fixed CI warning messages
v6:
    Remove extra space in the title before the colon.(DK)
    Rebase. (Jani)
v7: Use tabs for indenting the values.(Jani)
v8: Addressed dk's review comments.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Reviewed-by: default avatarDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: default avatarVathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: default avatarDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1530086910-15914-1-git-send-email-vathsala.nagaraju@intel.com
parent 7e7367d3

drivers/gpu/drm/i915/i915_debugfs.c

+48 −24
Original line number Diff line number Diff line
@@ -2592,8 +2592,12 @@ static const struct file_operations i915_guc_log_relay_fops = { 
	.release = i915_guc_log_relay_release,

};



static const char *psr2_live_status(u32 val)

static void

psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)

{

	u32 val, psr_status;



	if (dev_priv->psr.psr2_enabled) {

		static const char * const live_status[] = {

			"IDLE",

			"CAPTURE",
@@ -2607,12 +2611,36 @@ static const char *psr2_live_status(u32 val) 
			"BUF_ON",

			"TG_ON"

		};

		psr_status = I915_READ(EDP_PSR2_STATUS);

		val = (psr_status & EDP_PSR2_STATUS_STATE_MASK) >>

			EDP_PSR2_STATUS_STATE_SHIFT;

		if (val < ARRAY_SIZE(live_status)) {

			seq_printf(m, "Source PSR status: 0x%x [%s]\n",

				   psr_status, live_status[val]);

			return;

		}

	} else {

		static const char * const live_status[] = {

			"IDLE",

			"SRDONACK",

			"SRDENT",

			"BUFOFF",

			"BUFON",

			"AUXACK",

			"SRDOFFACK",

			"SRDENT_ON",

		};

		psr_status = I915_READ(EDP_PSR_STATUS);

		val = (psr_status & EDP_PSR_STATUS_STATE_MASK) >>

			EDP_PSR_STATUS_STATE_SHIFT;

		if (val < ARRAY_SIZE(live_status)) {

			seq_printf(m, "Source PSR status: 0x%x [%s]\n",

				   psr_status, live_status[val]);

			return;

		}

	}



	val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT;

	if (val < ARRAY_SIZE(live_status))

		return live_status[val];



	return "unknown";

	seq_printf(m, "Source PSR status: 0x%x [%s]\n", psr_status, "unknown");

}



static const char *psr_sink_status(u8 val)
@@ -2676,12 +2704,8 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) 


		seq_printf(m, "Performance_Counter: %u\n", psrperf);

	}

	if (dev_priv->psr.psr2_enabled) {

		u32 psr2 = I915_READ(EDP_PSR2_STATUS);



		seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",

			   psr2, psr2_live_status(psr2));

	}

	psr_source_status(dev_priv, m);



	if (dev_priv->psr.enabled) {

		struct drm_dp_aux *aux = &dev_priv->psr.enabled->aux;

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -4133,6 +4133,7 @@ enum { 


#define EDP_PSR_STATUS				_MMIO(dev_priv->psr_mmio_base + 0x40)

#define   EDP_PSR_STATUS_STATE_MASK		(7 << 29)

#define   EDP_PSR_STATUS_STATE_SHIFT		29

#define   EDP_PSR_STATUS_STATE_IDLE		(0 << 29)

#define   EDP_PSR_STATUS_STATE_SRDONACK		(1 << 29)

#define   EDP_PSR_STATUS_STATE_SRDENT		(2 << 29)