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Commit 0031fb96 authored by Tvrtko Ursulin's avatar Tvrtko Ursulin
Browse files

drm/i915: Assorted dev_priv cleanups 



A small selection of macros which can only accept dev_priv from
now on and a resulting trickle of fixups.

Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarDavid Weinehall <david.weinehall@linux.intel.com>
parent b42fe9ca

drivers/gpu/drm/i915/i915_drv.h

+17 −14
Original line number Diff line number Diff line
@@ -2527,28 +2527,31 @@ struct drm_i915_cmd_table { 
#define ALL_ENGINES	(~0)



#define HAS_ENGINE(dev_priv, id) \

	(!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id)))

	(!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))



#define HAS_BSD(dev_priv)	HAS_ENGINE(dev_priv, VCS)

#define HAS_BSD2(dev_priv)	HAS_ENGINE(dev_priv, VCS2)

#define HAS_BLT(dev_priv)	HAS_ENGINE(dev_priv, BCS)

#define HAS_VEBOX(dev_priv)	HAS_ENGINE(dev_priv, VECS)



#define HAS_LLC(dev)		(INTEL_INFO(dev)->has_llc)

#define HAS_SNOOP(dev)		(INTEL_INFO(dev)->has_snoop)

#define HAS_EDRAM(dev)		(!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))

#define HAS_LLC(dev_priv)	((dev_priv)->info.has_llc)

#define HAS_SNOOP(dev_priv)	((dev_priv)->info.has_snoop)

#define HAS_EDRAM(dev_priv)	(!!((dev_priv)->edram_cap & EDRAM_ENABLED))

#define HAS_WT(dev_priv)	((IS_HASWELL(dev_priv) || \

				 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))

#define HWS_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->hws_needs_physical)



#define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->has_hw_contexts)

#define HAS_LOGICAL_RING_CONTEXTS(dev)	(INTEL_INFO(dev)->has_logical_ring_contexts)

#define USES_PPGTT(dev)		(i915.enable_ppgtt)

#define USES_FULL_PPGTT(dev)	(i915.enable_ppgtt >= 2)

#define USES_FULL_48BIT_PPGTT(dev)	(i915.enable_ppgtt == 3)

#define HWS_NEEDS_PHYSICAL(dev_priv)	((dev_priv)->info.hws_needs_physical)



#define HAS_OVERLAY(dev)		(INTEL_INFO(dev)->has_overlay)

#define OVERLAY_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->overlay_needs_physical)

#define HAS_HW_CONTEXTS(dev_priv)	    ((dev_priv)->info.has_hw_contexts)

#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \

		((dev_priv)->info.has_logical_ring_contexts)

#define USES_PPGTT(dev_priv)		(i915.enable_ppgtt)

#define USES_FULL_PPGTT(dev_priv)	(i915.enable_ppgtt >= 2)

#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915.enable_ppgtt == 3)



#define HAS_OVERLAY(dev_priv)		 ((dev_priv)->info.has_overlay)

#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \

		((dev_priv)->info.overlay_needs_physical)



/* Early gen2 have a totally busted CS tlb and require pinned batches. */

#define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_845G(dev_priv))
@@ -2565,8 +2568,8 @@ struct drm_i915_cmd_table { 
 * legacy irq no. is shared with another device. The kernel then disables that

 * interrupt source and so prevents the other device from working properly.

 */

#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)

#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->has_gmbus_irq)

#define HAS_AUX_IRQ(dev_priv)   ((dev_priv)->info.gen >= 5)

#define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)



/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte

 * rows, which changed the alignment requirements and fence programming.

drivers/gpu/drm/i915/i915_gem.c

+7 −6
Original line number Diff line number Diff line
@@ -48,7 +48,7 @@ static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *o 
static bool cpu_cache_is_coherent(struct drm_device *dev,

				  enum i915_cache_level level)

{

	return HAS_LLC(dev) || level != I915_CACHE_NONE;

	return HAS_LLC(to_i915(dev)) || level != I915_CACHE_NONE;

}



static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
@@ -1757,7 +1757,7 @@ int i915_gem_fault(struct vm_area_struct *area, struct vm_fault *vmf) 
		goto err_rpm;



	/* Access to snoopable pages through the GTT is incoherent. */

	if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {

	if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) {

		ret = -EFAULT;

		goto err_unlock;

	}
@@ -3180,7 +3180,8 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 
		if (ret)

			return ret;



		if (!HAS_LLC(obj->base.dev) && cache_level != I915_CACHE_NONE) {

		if (!HAS_LLC(to_i915(obj->base.dev)) &&

		    cache_level != I915_CACHE_NONE) {

			/* Access to snoopable pages through the GTT is

			 * incoherent and on some machines causes a hard

			 * lockup. Relinquish the CPU mmaping to force
@@ -3884,7 +3885,7 @@ i915_gem_object_create(struct drm_device *dev, u64 size) 
	obj->base.write_domain = I915_GEM_DOMAIN_CPU;

	obj->base.read_domains = I915_GEM_DOMAIN_CPU;



	if (HAS_LLC(dev)) {

	if (HAS_LLC(dev_priv)) {

		/* On some devices, we can have the GPU use the LLC (the CPU

		 * cache) for about a 10% performance improvement

		 * compared to uncached.  Graphics requests other than
@@ -4130,7 +4131,7 @@ int i915_gem_suspend(struct drm_device *dev) 
	 * machines is a good idea, we don't - just in case it leaves the

	 * machine in an unusable condition.

	 */

	if (HAS_HW_CONTEXTS(dev)) {

	if (HAS_HW_CONTEXTS(dev_priv)) {

		int reset = intel_gpu_reset(dev_priv, ALL_ENGINES);

		WARN_ON(reset && reset != -ENODEV);

	}
@@ -4223,7 +4224,7 @@ i915_gem_init_hw(struct drm_device *dev) 
	/* Double layer security blanket, see i915_gem_init() */

	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);



	if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9)

	if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)

		I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));



	if (IS_HASWELL(dev_priv))

drivers/gpu/drm/i915/i915_gem_execbuffer.c

+2 −2
Original line number Diff line number Diff line
@@ -287,7 +287,7 @@ static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) 
	if (DBG_USE_CPU_RELOC)

		return DBG_USE_CPU_RELOC > 0;



	return (HAS_LLC(obj->base.dev) ||

	return (HAS_LLC(to_i915(obj->base.dev)) ||

		obj->base.write_domain == I915_GEM_DOMAIN_CPU ||

		obj->cache_level != I915_CACHE_NONE);

}
@@ -833,7 +833,7 @@ need_reloc_mappable(struct i915_vma *vma) 
		return false;



	/* See also use_cpu_reloc() */

	if (HAS_LLC(vma->obj->base.dev))

	if (HAS_LLC(to_i915(vma->obj->base.dev)))

		return false;



	if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU)

drivers/gpu/drm/i915/i915_gem_stolen.c

+2 −1
Original line number Diff line number Diff line
@@ -596,7 +596,8 @@ _i915_gem_object_create_stolen(struct drm_device *dev, 


	obj->stolen = stolen;

	obj->base.read_domains = I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT;

	obj->cache_level = HAS_LLC(dev) ? I915_CACHE_LLC : I915_CACHE_NONE;

	obj->cache_level = HAS_LLC(to_i915(dev)) ?

			   I915_CACHE_LLC : I915_CACHE_NONE;



	if (i915_gem_object_pin_pages(obj))

		goto cleanup;

drivers/gpu/drm/i915/i915_gem_userptr.c

+2 −1
Original line number Diff line number Diff line
@@ -753,12 +753,13 @@ static const struct drm_i915_gem_object_ops i915_gem_userptr_ops = { 
int

i915_gem_userptr_ioctl(struct drm_device *dev, void *data, struct drm_file *file)

{

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct drm_i915_gem_userptr *args = data;

	struct drm_i915_gem_object *obj;

	int ret;

	u32 handle;



	if (!HAS_LLC(dev) && !HAS_SNOOP(dev)) {

	if (!HAS_LLC(dev_priv) && !HAS_SNOOP(dev_priv)) {

		/* We cannot support coherent userptr objects on hw without

		 * LLC and broken snooping.

		 */