Commit 0019a40f authored Nov 17, 2022 by Nathan Chancellor Committed by Greg Kroah-Hartman Nov 23, 2022

x86/speculation: Use DECLARE_PER_CPU for x86_spec_ctrl_current



commit db886979683a8360ced9b24ab1125ad0c4d2cf76 upstream.

Clang warns:

  arch/x86/kernel/cpu/bugs.c:58:21: error: section attribute is specified on redeclared variable [-Werror,-Wsection]
  DEFINE_PER_CPU(u64, x86_spec_ctrl_current);
                      ^
  arch/x86/include/asm/nospec-branch.h:283:12: note: previous declaration is here
  extern u64 x86_spec_ctrl_current;
             ^
  1 error generated.

The declaration should be using DECLARE_PER_CPU instead so all
attributes stay in sync.

Cc: stable@vger.kernel.org
Fixes: fc02735b14ff ("KVM: VMX: Prevent guest RSB poisoning attacks with eIBRS")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Suleiman Souhlal <suleiman@google.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

parent 48eb8d6a

arch/x86/include/asm/nospec-branch.h

+2 −1

Original line number	Diff line number	Diff line
		@@ -11,6 +11,7 @@
		#include <asm/cpufeatures.h>
		#include <asm/msr-index.h>
		#include <asm/unwind_hints.h>
		#include <asm/percpu.h>

		/*
		* Fill the CPU return stack buffer.
		@@ -306,7 +307,7 @@ static inline void indirect_branch_prediction_barrier(void)

		/* The Intel SPEC CTRL MSR base value cache */
		extern u64 x86_spec_ctrl_base;
		extern u64 x86_spec_ctrl_current;
		DECLARE_PER_CPU(u64, x86_spec_ctrl_current);
		extern void write_spec_ctrl_current(u64 val, bool force);
		extern u64 spec_ctrl_current(void);