Loading arch/arm64/boot/dts/mediatek/mt6878.dts +2 −0 Original line number Diff line number Diff line Loading @@ -6755,6 +6755,7 @@ dispsys_config: dispsys-config@14000000 { "disp_token_cabc_eof1", "disp_token_cabc_eof3", "disp_dsi0_sof0", "disp_dsi0_cmd_done0", "disp_token_vfp_period0", "disp_token_disp_va_start0", "disp_token_disp_va_end0", Loading Loading @@ -6791,6 +6792,7 @@ dispsys_config: dispsys-config@14000000 { <&gce CMDQ_SYNC_TOKEN_CABC_EOF_1>, <&gce CMDQ_SYNC_TOKEN_CABC_EOF_3>, <&gce CMDQ_EVENT_DISPSYS_DISP_DSI0_SOF>, <&gce CMDQ_EVENT_DISPSYS_DISP_DSI0_CM_DONE_ENG_EVENT>, <&gce CMDQ_SYNC_TOKEN_VFP_PERIOD>, <&gce CMDQ_SYNC_TOKEN_DISP_VA_START>, <&gce CMDQ_SYNC_TOKEN_DISP_VA_END>, Loading drivers/gpu/drm/mediatek/mediatek_v2/mtk_drm_crtc.c +5 −0 Original line number Diff line number Diff line Loading @@ -16696,6 +16696,11 @@ static void mtk_crtc_get_event_name(struct mtk_drm_crtc *mtk_crtc, char *buf, sizeof(output_comp)); len = snprintf(buf, buf_len, "disp_%s_sof0", output_comp); break; case EVENT_DSI_CMD_DONE: mtk_crtc_get_output_comp_name(mtk_crtc, output_comp, sizeof(output_comp)); len = snprintf(buf, buf_len, "disp_%s_cmd_done0", output_comp); break; /*Msync 2.0*/ case EVENT_SYNC_TOKEN_VFP_PERIOD: len = snprintf(buf, buf_len, "disp_token_vfp_period%d", Loading drivers/gpu/drm/mediatek/mediatek_v2/mtk_drm_crtc.h +1 −0 Original line number Diff line number Diff line Loading @@ -587,6 +587,7 @@ enum CRTC_GCE_EVENT_TYPE { EVENT_STREAM_BLOCK, EVENT_CABC_EOF, EVENT_DSI_SOF, EVENT_DSI_CMD_DONE, /*Msync 2.0*/ EVENT_SYNC_TOKEN_VFP_PERIOD, EVENT_GPIO_TE0, Loading drivers/gpu/drm/mediatek/mediatek_v2/mtk_dsi.c +22 −8 Original line number Diff line number Diff line Loading @@ -6184,6 +6184,7 @@ static void mtk_dsi_cmdq_gce(struct mtk_dsi *dsi, struct cmdq_pkt *handle, DDPINFO("set cmdqaddr %u, val:%x, mask %x\n", DSI_CMDQ_SIZE, cmdq_size, CMDQ_SIZE); } static void mtk_dsi_cmdq_pack_gce(struct mtk_dsi *dsi, struct cmdq_pkt *handle, struct mtk_ddic_dsi_cmd *para_table) { Loading @@ -6197,11 +6198,13 @@ static void mtk_dsi_cmdq_pack_gce(struct mtk_dsi *dsi, struct cmdq_pkt *handle, unsigned int base_addr; struct mtk_ddp_comp *comp = &dsi->ddp_comp; struct mtk_panel_ext *panel_ext = dsi->ext; const u32 reg_cmdq_ofs = dsi->driver_data->reg_cmdq0_ofs; DDPINFO("%s +,\n", __func__); mtk_dsi_power_keep_gce(dsi, handle, true); if (!panel_ext || !panel_ext->params || !panel_ext->params->vdo_mix_mode_en) mtk_dsi_poll_for_idle(dsi, handle); if (mtk_dsi_is_cmd_mode(comp) && dsi->driver_data->require_phy_reset) Loading Loading @@ -6318,11 +6321,22 @@ static void mtk_dsi_cmdq_pack_gce(struct mtk_dsi *dsi, struct cmdq_pkt *handle, DDPINFO("total_cmdq_size = %d,DSI_CMDQ_SIZE=0x%x\n", total_cmdq_size, readl(dsi->regs + DSI_CMDQ_SIZE)); if (!panel_ext || !panel_ext->params || !panel_ext->params->vdo_mix_mode_en) { mtk_ddp_write_relaxed(comp, 0x0, DSI_START, handle); mtk_ddp_write_relaxed(comp, 0x1, DSI_START, handle); mtk_ddp_write_relaxed(comp, 0x0, DSI_START, handle); mtk_dsi_poll_for_idle(dsi, handle); } else { cmdq_pkt_clear_event(handle, comp->mtk_crtc->gce_obj.event[EVENT_DSI_CMD_DONE]); mtk_ddp_write_mask(comp, MIX_MODE, DSI_MODE_CTRL, MIX_MODE, handle); cmdq_pkt_wait_no_clear(handle, comp->mtk_crtc->gce_obj.event[EVENT_DSI_CMD_DONE]); mtk_ddp_write_mask(comp, 0, DSI_MODE_CTRL, MIX_MODE, handle); } if (para_table->is_hs == 1) mtk_ddp_write_mask(comp, 0, DSI_TXRX_CTRL, DIS_EOT, handle); Loading Loading @@ -10831,9 +10845,9 @@ static int mtk_dsi_io_cmd(struct mtk_ddp_comp *comp, struct cmdq_pkt *handle, panel_ext = mtk_dsi_get_panel_ext(comp); if (panel_ext && panel_ext->funcs && panel_ext->funcs->set_backlight_cmdq) panel_ext->funcs->set_backlight_cmdq(dsi, mipi_dsi_dcs_write_gce, && panel_ext->funcs->set_backlight_pack) panel_ext->funcs->set_backlight_pack(dsi, mtk_dsi_cmdq_pack_gce, handle, *(int *)params); } break; Loading drivers/gpu/drm/mediatek/mediatek_v2/mtk_panel_ext.h +4 −0 Original line number Diff line number Diff line Loading @@ -576,6 +576,8 @@ struct mtk_panel_params { bool dual_swap; unsigned int mode_switch_delay; bool vdo_mix_mode_en; }; struct mtk_panel_ext { Loading Loading @@ -609,6 +611,8 @@ struct mtk_panel_funcs { dic_dsi_read_cmd read_cb, struct DISP_PANEL_BASE_VOLTAGE *base_volageg); int (*set_backlight_cmdq)(void *dsi_drv, dcs_write_gce cb, void *handle, unsigned int level); int (*set_backlight_pack)(void *dsi_drv, dcs_write_gce_pack cb, void *handle, unsigned int level); int (*set_spr_cmdq)(void *dsi_drv, struct drm_panel *panel, dcs_grp_write_gce cb, void *handle, unsigned int en); int (*set_aod_light_mode)(void *dsi_drv, dcs_write_gce cb, Loading Loading
arch/arm64/boot/dts/mediatek/mt6878.dts +2 −0 Original line number Diff line number Diff line Loading @@ -6755,6 +6755,7 @@ dispsys_config: dispsys-config@14000000 { "disp_token_cabc_eof1", "disp_token_cabc_eof3", "disp_dsi0_sof0", "disp_dsi0_cmd_done0", "disp_token_vfp_period0", "disp_token_disp_va_start0", "disp_token_disp_va_end0", Loading Loading @@ -6791,6 +6792,7 @@ dispsys_config: dispsys-config@14000000 { <&gce CMDQ_SYNC_TOKEN_CABC_EOF_1>, <&gce CMDQ_SYNC_TOKEN_CABC_EOF_3>, <&gce CMDQ_EVENT_DISPSYS_DISP_DSI0_SOF>, <&gce CMDQ_EVENT_DISPSYS_DISP_DSI0_CM_DONE_ENG_EVENT>, <&gce CMDQ_SYNC_TOKEN_VFP_PERIOD>, <&gce CMDQ_SYNC_TOKEN_DISP_VA_START>, <&gce CMDQ_SYNC_TOKEN_DISP_VA_END>, Loading
drivers/gpu/drm/mediatek/mediatek_v2/mtk_drm_crtc.c +5 −0 Original line number Diff line number Diff line Loading @@ -16696,6 +16696,11 @@ static void mtk_crtc_get_event_name(struct mtk_drm_crtc *mtk_crtc, char *buf, sizeof(output_comp)); len = snprintf(buf, buf_len, "disp_%s_sof0", output_comp); break; case EVENT_DSI_CMD_DONE: mtk_crtc_get_output_comp_name(mtk_crtc, output_comp, sizeof(output_comp)); len = snprintf(buf, buf_len, "disp_%s_cmd_done0", output_comp); break; /*Msync 2.0*/ case EVENT_SYNC_TOKEN_VFP_PERIOD: len = snprintf(buf, buf_len, "disp_token_vfp_period%d", Loading
drivers/gpu/drm/mediatek/mediatek_v2/mtk_drm_crtc.h +1 −0 Original line number Diff line number Diff line Loading @@ -587,6 +587,7 @@ enum CRTC_GCE_EVENT_TYPE { EVENT_STREAM_BLOCK, EVENT_CABC_EOF, EVENT_DSI_SOF, EVENT_DSI_CMD_DONE, /*Msync 2.0*/ EVENT_SYNC_TOKEN_VFP_PERIOD, EVENT_GPIO_TE0, Loading
drivers/gpu/drm/mediatek/mediatek_v2/mtk_dsi.c +22 −8 Original line number Diff line number Diff line Loading @@ -6184,6 +6184,7 @@ static void mtk_dsi_cmdq_gce(struct mtk_dsi *dsi, struct cmdq_pkt *handle, DDPINFO("set cmdqaddr %u, val:%x, mask %x\n", DSI_CMDQ_SIZE, cmdq_size, CMDQ_SIZE); } static void mtk_dsi_cmdq_pack_gce(struct mtk_dsi *dsi, struct cmdq_pkt *handle, struct mtk_ddic_dsi_cmd *para_table) { Loading @@ -6197,11 +6198,13 @@ static void mtk_dsi_cmdq_pack_gce(struct mtk_dsi *dsi, struct cmdq_pkt *handle, unsigned int base_addr; struct mtk_ddp_comp *comp = &dsi->ddp_comp; struct mtk_panel_ext *panel_ext = dsi->ext; const u32 reg_cmdq_ofs = dsi->driver_data->reg_cmdq0_ofs; DDPINFO("%s +,\n", __func__); mtk_dsi_power_keep_gce(dsi, handle, true); if (!panel_ext || !panel_ext->params || !panel_ext->params->vdo_mix_mode_en) mtk_dsi_poll_for_idle(dsi, handle); if (mtk_dsi_is_cmd_mode(comp) && dsi->driver_data->require_phy_reset) Loading Loading @@ -6318,11 +6321,22 @@ static void mtk_dsi_cmdq_pack_gce(struct mtk_dsi *dsi, struct cmdq_pkt *handle, DDPINFO("total_cmdq_size = %d,DSI_CMDQ_SIZE=0x%x\n", total_cmdq_size, readl(dsi->regs + DSI_CMDQ_SIZE)); if (!panel_ext || !panel_ext->params || !panel_ext->params->vdo_mix_mode_en) { mtk_ddp_write_relaxed(comp, 0x0, DSI_START, handle); mtk_ddp_write_relaxed(comp, 0x1, DSI_START, handle); mtk_ddp_write_relaxed(comp, 0x0, DSI_START, handle); mtk_dsi_poll_for_idle(dsi, handle); } else { cmdq_pkt_clear_event(handle, comp->mtk_crtc->gce_obj.event[EVENT_DSI_CMD_DONE]); mtk_ddp_write_mask(comp, MIX_MODE, DSI_MODE_CTRL, MIX_MODE, handle); cmdq_pkt_wait_no_clear(handle, comp->mtk_crtc->gce_obj.event[EVENT_DSI_CMD_DONE]); mtk_ddp_write_mask(comp, 0, DSI_MODE_CTRL, MIX_MODE, handle); } if (para_table->is_hs == 1) mtk_ddp_write_mask(comp, 0, DSI_TXRX_CTRL, DIS_EOT, handle); Loading Loading @@ -10831,9 +10845,9 @@ static int mtk_dsi_io_cmd(struct mtk_ddp_comp *comp, struct cmdq_pkt *handle, panel_ext = mtk_dsi_get_panel_ext(comp); if (panel_ext && panel_ext->funcs && panel_ext->funcs->set_backlight_cmdq) panel_ext->funcs->set_backlight_cmdq(dsi, mipi_dsi_dcs_write_gce, && panel_ext->funcs->set_backlight_pack) panel_ext->funcs->set_backlight_pack(dsi, mtk_dsi_cmdq_pack_gce, handle, *(int *)params); } break; Loading
drivers/gpu/drm/mediatek/mediatek_v2/mtk_panel_ext.h +4 −0 Original line number Diff line number Diff line Loading @@ -576,6 +576,8 @@ struct mtk_panel_params { bool dual_swap; unsigned int mode_switch_delay; bool vdo_mix_mode_en; }; struct mtk_panel_ext { Loading Loading @@ -609,6 +611,8 @@ struct mtk_panel_funcs { dic_dsi_read_cmd read_cb, struct DISP_PANEL_BASE_VOLTAGE *base_volageg); int (*set_backlight_cmdq)(void *dsi_drv, dcs_write_gce cb, void *handle, unsigned int level); int (*set_backlight_pack)(void *dsi_drv, dcs_write_gce_pack cb, void *handle, unsigned int level); int (*set_spr_cmdq)(void *dsi_drv, struct drm_panel *panel, dcs_grp_write_gce cb, void *handle, unsigned int en); int (*set_aod_light_mode)(void *dsi_drv, dcs_write_gce cb, Loading