Loading drivers/platform/msm/ep_pcie/ep_pcie_com.h +6 −2 Original line number Diff line number Diff line Loading @@ -47,9 +47,13 @@ #define PCIE20_PARF_CLKREQ_OVERRIDE 0x2B0 #define PCIE20_PARF_CLKREQ_IN_OVERRIDE_STS BIT(5) #define PCIE20_PARF_CLKREQ_OE_OVERRIDE_STS BIT(4) #define PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL BIT(3) #define PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL_MASK BIT(3) #define PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL_ASSERT 0 #define PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL_DEASSERT 1 #define PCIE20_PARF_CLKREQ_OE_OVERRIDE_VAL BIT(2) #define PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE BIT(1) #define PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE_MASK BIT(1) #define PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE_DIS 0 #define PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE_EN 1 #define PCIE20_PARF_CLKREQ_OE_OVERRIDE_ENABLE BIT(0) #define PCIE20_PARF_SLV_ADDR_MSB_CTRL 0x2C0 Loading drivers/platform/msm/ep_pcie/ep_pcie_core.c +8 −4 Original line number Diff line number Diff line Loading @@ -1440,14 +1440,18 @@ static int ep_pcie_core_clkreq_override(bool config) if (config) { ep_pcie_write_reg_field(dev->parf, PCIE20_PARF_CLKREQ_OVERRIDE, PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL, BIT(3)); PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL_MASK, PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL_DEASSERT); ep_pcie_write_reg_field(dev->parf, PCIE20_PARF_CLKREQ_OVERRIDE, PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE, BIT(1)); PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE_MASK, PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE_EN); } else { ep_pcie_write_reg_field(dev->parf, PCIE20_PARF_CLKREQ_OVERRIDE, PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE, 0); PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE_MASK, PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE_DIS); ep_pcie_write_reg_field(dev->parf, PCIE20_PARF_CLKREQ_OVERRIDE, PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL, 0); PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL_MASK, PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL_ASSERT); } return 0; Loading Loading
drivers/platform/msm/ep_pcie/ep_pcie_com.h +6 −2 Original line number Diff line number Diff line Loading @@ -47,9 +47,13 @@ #define PCIE20_PARF_CLKREQ_OVERRIDE 0x2B0 #define PCIE20_PARF_CLKREQ_IN_OVERRIDE_STS BIT(5) #define PCIE20_PARF_CLKREQ_OE_OVERRIDE_STS BIT(4) #define PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL BIT(3) #define PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL_MASK BIT(3) #define PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL_ASSERT 0 #define PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL_DEASSERT 1 #define PCIE20_PARF_CLKREQ_OE_OVERRIDE_VAL BIT(2) #define PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE BIT(1) #define PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE_MASK BIT(1) #define PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE_DIS 0 #define PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE_EN 1 #define PCIE20_PARF_CLKREQ_OE_OVERRIDE_ENABLE BIT(0) #define PCIE20_PARF_SLV_ADDR_MSB_CTRL 0x2C0 Loading
drivers/platform/msm/ep_pcie/ep_pcie_core.c +8 −4 Original line number Diff line number Diff line Loading @@ -1440,14 +1440,18 @@ static int ep_pcie_core_clkreq_override(bool config) if (config) { ep_pcie_write_reg_field(dev->parf, PCIE20_PARF_CLKREQ_OVERRIDE, PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL, BIT(3)); PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL_MASK, PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL_DEASSERT); ep_pcie_write_reg_field(dev->parf, PCIE20_PARF_CLKREQ_OVERRIDE, PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE, BIT(1)); PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE_MASK, PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE_EN); } else { ep_pcie_write_reg_field(dev->parf, PCIE20_PARF_CLKREQ_OVERRIDE, PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE, 0); PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE_MASK, PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE_DIS); ep_pcie_write_reg_field(dev->parf, PCIE20_PARF_CLKREQ_OVERRIDE, PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL, 0); PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL_MASK, PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL_ASSERT); } return 0; Loading