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Commit ff00d85b authored by Rodrigo Vivi's avatar Rodrigo Vivi
Browse files

Merge tag 'gvt-next-2019-01-24' of https://github.com/intel/gvt-linux into drm-intel-next-queued 



gvt-next-2019-01-24

- split kvmgt as seperate module (Zhenyu)
- Coffeelake GVT support (Fred)
- const treatment and change for kernel type (Jani)

Signed-off-by: default avatarRodrigo Vivi <vivijim@rdvivi-cozumel.jf.intel.com>
From: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190124054048.GO7203@zhen-hp.sh.intel.com
parents 0cdc1d07 2e679d48

drivers/gpu/drm/i915/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -200,3 +200,4 @@ endif 
i915-y += intel_lpe_audio.o



obj-$(CONFIG_DRM_I915) += i915.o

obj-$(CONFIG_DRM_I915_GVT_KVMGT) += gvt/kvmgt.o

drivers/gpu/drm/i915/gvt/Makefile

+0 −1
Original line number Diff line number Diff line
@@ -7,4 +7,3 @@ GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \ 


ccflags-y				+= -I$(src) -I$(src)/$(GVT_DIR)

i915-y					+= $(addprefix $(GVT_DIR)/, $(GVT_SOURCE))
 
obj-$(CONFIG_DRM_I915_GVT_KVMGT)	+= $(GVT_DIR)/kvmgt.o

drivers/gpu/drm/i915/gvt/cmd_parser.c

+39 −44
Original line number Diff line number Diff line
@@ -55,10 +55,10 @@ struct sub_op_bits { 
	int low;

};

struct decode_info {

	char *name;

	const char *name;

	int op_len;

	int nr_sub_op;

	struct sub_op_bits *sub_op;

	const struct sub_op_bits *sub_op;

};



#define   MAX_CMD_BUDGET			0x7fffffff
@@ -375,7 +375,7 @@ typedef int (*parser_cmd_handler)(struct parser_exec_state *s); 
#define ADDR_FIX_5(x1, x2, x3, x4, x5)  (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))



struct cmd_info {

	char *name;

	const char *name;

	u32 opcode;



#define F_LEN_MASK	(1U<<0)
@@ -399,10 +399,10 @@ struct cmd_info { 
#define R_VECS	(1 << VECS)

#define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)

	/* rings that support this cmd: BLT/RCS/VCS/VECS */

	uint16_t rings;

	u16 rings;



	/* devices that support this cmd: SNB/IVB/HSW/... */

	uint16_t devices;

	u16 devices;



	/* which DWords are address that need fix up.

	 * bit 0 means a 32-bit non address operand in command
@@ -412,20 +412,20 @@ struct cmd_info { 
	 * No matter the address length, each address only takes

	 * one bit in the bitmap.

	 */

	uint16_t addr_bitmap;

	u16 addr_bitmap;



	/* flag == F_LEN_CONST : command length

	 * flag == F_LEN_VAR : length bias bits

	 * Note: length is in DWord

	 */

	uint8_t	len;

	u8 len;



	parser_cmd_handler handler;

};



struct cmd_entry {

	struct hlist_node hlist;

	struct cmd_info *info;

	const struct cmd_info *info;

};



enum {
@@ -474,7 +474,7 @@ struct parser_exec_state { 
	int saved_buf_addr_type;

	bool is_ctx_wa;



	struct cmd_info *info;

	const struct cmd_info *info;



	struct intel_vgpu_workload *workload;

};
@@ -485,12 +485,12 @@ struct parser_exec_state { 
static unsigned long bypass_scan_mask = 0;



/* ring ALL, type = 0 */

static struct sub_op_bits sub_op_mi[] = {

static const struct sub_op_bits sub_op_mi[] = {

	{31, 29},

	{28, 23},

};



static struct decode_info decode_info_mi = {

static const struct decode_info decode_info_mi = {

	"MI",

	OP_LEN_MI,

	ARRAY_SIZE(sub_op_mi),
@@ -498,12 +498,12 @@ static struct decode_info decode_info_mi = { 
};



/* ring RCS, command type 2 */

static struct sub_op_bits sub_op_2d[] = {

static const struct sub_op_bits sub_op_2d[] = {

	{31, 29},

	{28, 22},

};



static struct decode_info decode_info_2d = {

static const struct decode_info decode_info_2d = {

	"2D",

	OP_LEN_2D,

	ARRAY_SIZE(sub_op_2d),
@@ -511,14 +511,14 @@ static struct decode_info decode_info_2d = { 
};



/* ring RCS, command type 3 */

static struct sub_op_bits sub_op_3d_media[] = {

static const struct sub_op_bits sub_op_3d_media[] = {

	{31, 29},

	{28, 27},

	{26, 24},

	{23, 16},

};



static struct decode_info decode_info_3d_media = {

static const struct decode_info decode_info_3d_media = {

	"3D_Media",

	OP_LEN_3D_MEDIA,

	ARRAY_SIZE(sub_op_3d_media),
@@ -526,7 +526,7 @@ static struct decode_info decode_info_3d_media = { 
};



/* ring VCS, command type 3 */

static struct sub_op_bits sub_op_mfx_vc[] = {

static const struct sub_op_bits sub_op_mfx_vc[] = {

	{31, 29},

	{28, 27},

	{26, 24},
@@ -534,7 +534,7 @@ static struct sub_op_bits sub_op_mfx_vc[] = { 
	{20, 16},

};



static struct decode_info decode_info_mfx_vc = {

static const struct decode_info decode_info_mfx_vc = {

	"MFX_VC",

	OP_LEN_MFX_VC,

	ARRAY_SIZE(sub_op_mfx_vc),
@@ -542,7 +542,7 @@ static struct decode_info decode_info_mfx_vc = { 
};



/* ring VECS, command type 3 */

static struct sub_op_bits sub_op_vebox[] = {

static const struct sub_op_bits sub_op_vebox[] = {

	{31, 29},

	{28, 27},

	{26, 24},
@@ -550,14 +550,14 @@ static struct sub_op_bits sub_op_vebox[] = { 
	{20, 16},

};



static struct decode_info decode_info_vebox = {

static const struct decode_info decode_info_vebox = {

	"VEBOX",

	OP_LEN_VEBOX,

	ARRAY_SIZE(sub_op_vebox),

	sub_op_vebox,

};



static struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {

static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {

	[RCS] = {

		&decode_info_mi,

		NULL,
@@ -616,7 +616,7 @@ static struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = { 


static inline u32 get_opcode(u32 cmd, int ring_id)

{

	struct decode_info *d_info;

	const struct decode_info *d_info;



	d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];

	if (d_info == NULL)
@@ -625,7 +625,7 @@ static inline u32 get_opcode(u32 cmd, int ring_id) 
	return cmd >> (32 - d_info->op_len);

}



static inline struct cmd_info *find_cmd_entry(struct intel_gvt *gvt,

static inline const struct cmd_info *find_cmd_entry(struct intel_gvt *gvt,

		unsigned int opcode, int ring_id)

{

	struct cmd_entry *e;
@@ -638,7 +638,7 @@ static inline struct cmd_info *find_cmd_entry(struct intel_gvt *gvt, 
	return NULL;

}



static inline struct cmd_info *get_cmd_info(struct intel_gvt *gvt,

static inline const struct cmd_info *get_cmd_info(struct intel_gvt *gvt,

		u32 cmd, int ring_id)

{

	u32 opcode;
@@ -657,7 +657,7 @@ static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low) 


static inline void print_opcode(u32 cmd, int ring_id)

{

	struct decode_info *d_info;

	const struct decode_info *d_info;

	int i;



	d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
@@ -776,7 +776,7 @@ static inline int ip_gma_advance(struct parser_exec_state *s, 
	return 0;

}



static inline int get_cmd_length(struct cmd_info *info, u32 cmd)

static inline int get_cmd_length(const struct cmd_info *info, u32 cmd)

{

	if ((info->flag & F_LEN_MASK) == F_LEN_CONST)

		return info->len;
@@ -901,7 +901,8 @@ static int cmd_reg_handler(struct parser_exec_state *s, 
	 * It's good enough to support initializing mmio by lri command in

	 * vgpu inhibit context on KBL.

	 */

	if (IS_KABYLAKE(s->vgpu->gvt->dev_priv) &&

	if ((IS_KABYLAKE(s->vgpu->gvt->dev_priv)

		|| IS_COFFEELAKE(s->vgpu->gvt->dev_priv)) &&

			intel_gvt_mmio_is_in_ctx(gvt, offset) &&

			!strncmp(cmd, "lri", 3)) {

		intel_gvt_hypervisor_read_gpa(s->vgpu,
@@ -1280,9 +1281,7 @@ static int gen8_check_mi_display_flip(struct parser_exec_state *s, 
	if (!info->async_flip)

		return 0;



	if (IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv)

		|| IS_BROXTON(dev_priv)) {

	if (INTEL_GEN(dev_priv) >= 9) {

		stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);

		tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &

				GENMASK(12, 10)) >> 10;
@@ -1310,9 +1309,7 @@ static int gen8_update_plane_mmio_from_mi_display_flip( 


	set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),

		      info->surf_val << 12);

	if (IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv)

		|| IS_BROXTON(dev_priv)) {

	if (INTEL_GEN(dev_priv) >= 9) {

		set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),

			      info->stride_val);

		set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
@@ -1336,9 +1333,7 @@ static int decode_mi_display_flip(struct parser_exec_state *s, 


	if (IS_BROADWELL(dev_priv))

		return gen8_decode_mi_display_flip(s, info);

	if (IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv)

		|| IS_BROXTON(dev_priv))

	if (INTEL_GEN(dev_priv) >= 9)

		return skl_decode_mi_display_flip(s, info);



	return -ENODEV;
@@ -1643,8 +1638,8 @@ static int batch_buffer_needs_scan(struct parser_exec_state *s) 
static int find_bb_size(struct parser_exec_state *s, unsigned long *bb_size)

{

	unsigned long gma = 0;

	struct cmd_info *info;

	uint32_t cmd_len = 0;

	const struct cmd_info *info;

	u32 cmd_len = 0;

	bool bb_end = false;

	struct intel_vgpu *vgpu = s->vgpu;

	u32 cmd;
@@ -1842,7 +1837,7 @@ static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s) 


static int mi_noop_index;



static struct cmd_info cmd_info[] = {

static const struct cmd_info cmd_info[] = {

	{"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},



	{"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL,
@@ -2521,7 +2516,7 @@ static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e) 
static int cmd_parser_exec(struct parser_exec_state *s)

{

	struct intel_vgpu *vgpu = s->vgpu;

	struct cmd_info *info;

	const struct cmd_info *info;

	u32 cmd;

	int ret = 0;
@@ -2683,7 +2678,7 @@ static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) 
					I915_GTT_PAGE_SIZE)))

		return -EINVAL;



	ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(uint32_t);

	ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(u32);

	ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,

			PAGE_SIZE);

	gma_head = wa_ctx->indirect_ctx.guest_gma;
@@ -2850,7 +2845,7 @@ static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx) 


static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)

{

	uint32_t per_ctx_start[CACHELINE_DWORDS] = {0};

	u32 per_ctx_start[CACHELINE_DWORDS] = {0};

	unsigned char *bb_start_sva;



	if (!wa_ctx->per_ctx.valid)
@@ -2895,10 +2890,10 @@ int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) 
	return 0;

}



static struct cmd_info *find_cmd_entry_any_ring(struct intel_gvt *gvt,

static const struct cmd_info *find_cmd_entry_any_ring(struct intel_gvt *gvt,

		unsigned int opcode, unsigned long rings)

{

	struct cmd_info *info = NULL;

	const struct cmd_info *info = NULL;

	unsigned int ring;



	for_each_set_bit(ring, &rings, I915_NUM_ENGINES) {
@@ -2913,7 +2908,7 @@ static int init_cmd_table(struct intel_gvt *gvt) 
{

	int i;

	struct cmd_entry *e;

	struct cmd_info	*info;

	const struct cmd_info *info;

	unsigned int gen_type;



	gen_type = intel_gvt_get_device_type(gvt);

drivers/gpu/drm/i915/gvt/display.c

+8 −4
Original line number Diff line number Diff line
@@ -198,7 +198,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 
			SDE_PORTC_HOTPLUG_CPT |

			SDE_PORTD_HOTPLUG_CPT);



	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ||

	    IS_COFFEELAKE(dev_priv)) {

		vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |

				SDE_PORTE_HOTPLUG_SPT);

		vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
@@ -273,7 +274,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 
		vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;

	}



	if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&

	if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ||

	     IS_COFFEELAKE(dev_priv)) &&

			intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {

		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;

	}
@@ -453,7 +455,8 @@ void intel_vgpu_clean_display(struct intel_vgpu *vgpu) 
{

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;



	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ||

	    IS_COFFEELAKE(dev_priv))

		clean_virtual_dp_monitor(vgpu, PORT_D);

	else

		clean_virtual_dp_monitor(vgpu, PORT_B);
@@ -476,7 +479,8 @@ int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution) 


	intel_vgpu_init_i2c_edid(vgpu);



	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ||

	    IS_COFFEELAKE(dev_priv))

		return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,

						resolution);

	else

drivers/gpu/drm/i915/gvt/dmabuf.c

+1 −4
Original line number Diff line number Diff line
@@ -29,7 +29,6 @@ 
 */



#include <linux/dma-buf.h>

#include <drm/drmP.h>

#include <linux/vfio.h>



#include "i915_drv.h"
@@ -164,9 +163,7 @@ static struct drm_i915_gem_object *vgpu_create_gem(struct drm_device *dev, 


	obj->read_domains = I915_GEM_DOMAIN_GTT;

	obj->write_domain = 0;

	if (IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv)

		|| IS_BROXTON(dev_priv)) {

	if (INTEL_GEN(dev_priv) >= 9) {

		unsigned int tiling_mode = 0;

		unsigned int stride = 0;