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Commit fef2d7f6 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: Add USB2 virtio clocks for sa8195p"

parents e2e067d6 3e06d3c4

drivers/clk/qcom/virtio_clk_sa8195p.c

+16 −0
Original line number Diff line number Diff line
@@ -53,6 +53,15 @@ static const char * const sa8195p_gcc_virtio_clocks[] = { 
	[GCC_USB3_SEC_PHY_PIPE_CLK] = "gcc_usb3_sec_phy_pipe_clk",

	[GCC_USB3_SEC_CLKREF_CLK] = "gcc_usb3_sec_clkref_en",

	[GCC_USB3_SEC_PHY_COM_AUX_CLK] = "gcc_usb3_sec_phy_com_aux_clk",

	[GCC_USB30_MP_MASTER_CLK] = "gcc_usb30_mp_master_clk",

	[GCC_CFG_NOC_USB3_MP_AXI_CLK] = "gcc_cfg_noc_usb3_mp_axi_clk",

	[GCC_AGGRE_USB3_MP_AXI_CLK] = "gcc_aggre_usb3_mp_axi_clk",

	[GCC_USB30_MP_MOCK_UTMI_CLK] = "gcc_usb30_mp_mock_utmi_clk",

	[GCC_USB30_MP_SLEEP_CLK] = "gcc_usb30_mp_sleep_clk",

	[GCC_USB3_MP_PHY_AUX_CLK] = "gcc_usb3_mp_phy_aux_clk",

	[GCC_USB3_MP_PHY_PIPE_0_CLK] = "gcc_usb3_mp_phy_pipe_0_clk",

	[GCC_USB3_MP_PHY_COM_AUX_CLK] = "gcc_usb3_mp_phy_com_aux_clk",

	[GCC_USB3_MP_PHY_PIPE_1_CLK] = "gcc_usb3_mp_phy_pipe_1_clk",

	[GCC_PCIE_0_PIPE_CLK] = "gcc_pcie_0_pipe_clk",

	[GCC_PCIE_0_AUX_CLK] = "gcc_pcie_0_aux_clk",

	[GCC_PCIE_0_CFG_AHB_CLK] = "gcc_pcie_0_cfg_ahb_clk",
@@ -105,8 +114,15 @@ static const char * const sa8195p_gcc_virtio_clocks[] = { 
static const char * const sa8195p_gcc_virtio_resets[] = {

	[GCC_QUSB2PHY_PRIM_BCR] = "gcc_qusb2phy_prim_bcr",

	[GCC_QUSB2PHY_SEC_BCR] = "gcc_qusb2phy_sec_bcr",

	[GCC_QUSB2PHY_MP0_BCR] = "gcc_qusb2phy_mp0_bcr",

	[GCC_QUSB2PHY_MP1_BCR] = "gcc_qusb2phy_mp1_bcr",

	[GCC_USB30_PRIM_BCR] = "gcc_usb30_prim_master_clk",

	[GCC_USB30_SEC_BCR] = "gcc_usb30_sec_master_clk",

	[GCC_USB30_MP_BCR] = "gcc_usb30_mp_master_clk",

	[GCC_USB3_UNIPHY_MP0_BCR] = "gcc_usb3_uniphy_mp0_bcr",

	[GCC_USB3UNIPHY_PHY_MP0_BCR] = "gcc_usb3uniphy_phy_mp0_bcr",

	[GCC_USB3_UNIPHY_MP1_BCR] = "gcc_usb3_uniphy_mp1_bcr",

	[GCC_USB3UNIPHY_PHY_MP1_BCR] = "gcc_usb3uniphy_phy_mp1_bcr",

	[GCC_PCIE_0_BCR] = "gcc_pcie_0_mstr_axi_clk",

	[GCC_PCIE_0_PHY_BCR] = "gcc_pcie_0_phy_bcr",

	[GCC_PCIE_1_BCR] = "gcc_pcie_1_mstr_axi_clk",