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Commit fea0b085 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-typo', 'clk-json-schema', 'clk-mtk-2712-eco' and 'clk-rockchip' into clk-next 

 - Convert a few clk bindings to JSON schema format
 - 3rd ECO fix for Mediatek MT2712 SoCs

* clk-typo:
  clk: samsung: fix typo

* clk-json-schema:
  dt-bindings: clock: Convert fixed-factor-clock to json-schema
  dt-bindings: clock: Convert fixed-clock binding to json-schema

* clk-mtk-2712-eco:
  clk: mediatek: update clock driver of MT2712
  dt-bindings: clock: add clock for MT2712

* clk-rockchip:
  clk: rockchip: add CLK_SET_RATE_PARENT for rk3066 lcdc dclks
  clk: rockchip: fix frac settings of GPLL clock for rk3328
parents bd5e2ea2 463a554b f79bae16 51ff86dd a49ba41c

Documentation/devicetree/bindings/clock/fixed-clock.txt

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Binding for simple fixed-rate clock sources.



This binding uses the common clock binding[1].



[1] Documentation/devicetree/bindings/clock/clock-bindings.txt



Required properties:

- compatible : shall be "fixed-clock".

- #clock-cells : from common clock binding; shall be set to 0.

- clock-frequency : frequency of clock in Hz. Should be a single cell.



Optional properties:

- clock-accuracy : accuracy of clock in ppb (parts per billion).

		   Should be a single cell.

- clock-output-names : From common clock binding.



Example:

	clock {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <1000000000>;

		clock-accuracy = <100>;

	};

Documentation/devicetree/bindings/clock/fixed-clock.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/fixed-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Binding for simple fixed-rate clock sources



maintainers:

  - Michael Turquette <mturquette@baylibre.com>

  - Stephen Boyd <sboyd@kernel.org>



properties:

  compatible:

    const: fixed-clock



  "#clock-cells":

    const: 0



  clock-frequency: true



  clock-accuracy:

    description: accuracy of clock in ppb (parts per billion).

    $ref: /schemas/types.yaml#/definitions/uint32



  clock-output-names:

    maxItems: 1



required:

  - compatible

  - "#clock-cells"

  - clock-frequency



additionalProperties: false



examples:

  - |

    clock {

      compatible = "fixed-clock";

      #clock-cells = <0>;

      clock-frequency = <1000000000>;

      clock-accuracy = <100>;

    };

...

Documentation/devicetree/bindings/clock/fixed-factor-clock.txt

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Binding for simple fixed factor rate clock sources.



This binding uses the common clock binding[1].



[1] Documentation/devicetree/bindings/clock/clock-bindings.txt



Required properties:

- compatible : shall be "fixed-factor-clock".

- #clock-cells : from common clock binding; shall be set to 0.

- clock-div: fixed divider.

- clock-mult: fixed multiplier.

- clocks: parent clock.



Optional properties:

- clock-output-names : From common clock binding.



Some clocks that require special treatments are also handled by that

driver, with the compatibles:

  - allwinner,sun4i-a10-pll3-2x-clk



Example:

	clock {

		compatible = "fixed-factor-clock";

		clocks = <&parentclk>;

		#clock-cells = <0>;

		clock-div = <2>;

		clock-mult = <1>;

	};

Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Binding for simple fixed factor rate clock sources



maintainers:

  - Michael Turquette <mturquette@baylibre.com>

  - Stephen Boyd <sboyd@kernel.org>



properties:

  compatible:

    enum:

      - allwinner,sun4i-a10-pll3-2x-clk

      - fixed-factor-clock



  "#clock-cells":

    const: 0



  clocks:

    maxItems: 1



  clock-div:

    description: Fixed divider

    allOf:

      - $ref: /schemas/types.yaml#/definitions/uint32

      - minimum: 1



  clock-mult:

    description: Fixed multiplier

    $ref: /schemas/types.yaml#/definitions/uint32



  clock-output-names:

    maxItems: 1



required:

  - compatible

  - clocks

  - "#clock-cells"

  - clock-div

  - clock-mult



additionalProperties: false



examples:

  - |

    clock {

      compatible = "fixed-factor-clock";

      clocks = <&parentclk>;

      #clock-cells = <0>;

      clock-div = <2>;

      clock-mult = <1>;

    };

...

drivers/clk/mediatek/clk-mt2712.c

+6 −2
Original line number Diff line number Diff line
@@ -223,6 +223,8 @@ static const struct mtk_fixed_factor top_divs[] = { 
		4),

	FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1_ck", 1,

		3),

	FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2_ck", 1,

		3),

};



static const char * const axi_parents[] = {
@@ -594,7 +596,8 @@ static const char * const a1sys_hp_parents[] = { 
	"apll1_ck",

	"apll1_d2",

	"apll1_d4",

	"apll1_d8"

	"apll1_d8",

	"apll1_d3"

};



static const char * const a2sys_hp_parents[] = {
@@ -602,7 +605,8 @@ static const char * const a2sys_hp_parents[] = { 
	"apll2_ck",

	"apll2_d2",

	"apll2_d4",

	"apll2_d8"

	"apll2_d8",

	"apll2_d3"

};



static const char * const asm_l_parents[] = {