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Commit fe159bfa authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "firmware: qcom_scm-32: Use SMC arch wrappers"

parents 37d4fdf7 b2c9a7b7

drivers/firmware/Makefile

+0 −1
Original line number Diff line number Diff line
@@ -20,7 +20,6 @@ obj-$(CONFIG_FW_CFG_SYSFS) += qemu_fw_cfg.o 
obj-$(CONFIG_QCOM_SCM)		+= qcom_scm.o

obj-$(CONFIG_QCOM_SCM_64)	+= qcom_scm-64.o

obj-$(CONFIG_QCOM_SCM_32)	+= qcom_scm-32.o

CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch armv7-a\n.arch_extension sec,-DREQUIRES_SEC=1) -march=armv7-a

obj-$(CONFIG_TI_SCI_PROTOCOL)	+= ti_sci.o

obj-$(CONFIG_TRUSTED_FOUNDATIONS) += trusted_foundations.o

obj-$(CONFIG_TURRIS_MOX_RWTM)	+= turris-mox-rwtm.o

drivers/firmware/qcom_scm-32.c

+17 −54
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 
#include <linux/errno.h>

#include <linux/err.h>

#include <linux/qcom_scm.h>

#include <linux/arm-smccc.h>

#include <linux/dma-mapping.h>



#include "qcom_scm.h"
@@ -124,25 +125,13 @@ static inline void *legacy_get_response_buffer( 
static u32 __qcom_scm_call_do(u32 cmd_addr)

{

	int context_id;

	register u32 r0 asm("r0") = 1;

	register u32 r1 asm("r1") = (u32)&context_id;

	register u32 r2 asm("r2") = cmd_addr;

	struct arm_smccc_res res;

	do {

		asm volatile(

			__asmeq("%0", "r0")

			__asmeq("%1", "r0")

			__asmeq("%2", "r1")

			__asmeq("%3", "r2")

#ifdef REQUIRES_SEC

			".arch_extension sec\n"

#endif

			"smc	#0	@ switch to secure world\n"

			: "=r" (r0)

			: "r" (r0), "r" (r1), "r" (r2)

			: "r3", "r12");

	} while (r0 == QCOM_SCM_INTERRUPTED);



	return r0;

		arm_smccc_smc(1, (unsigned long)&context_id, cmd_addr,

			      0, 0, 0, 0, 0, &res);

	} while (res.a0 == QCOM_SCM_INTERRUPTED);



	return res.a0;

}



/**
@@ -240,24 +229,12 @@ static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id, 
static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1)

{

	int context_id;

	struct arm_smccc_res res;



	arm_smccc_smc(LEGACY_ATOMIC_ID(svc, cmd, 1), (unsigned long)&context_id,

		      arg1, 0, 0, 0, 0, 0, &res);



	register u32 r0 asm("r0") = LEGACY_ATOMIC_ID(svc, cmd, 1);

	register u32 r1 asm("r1") = (u32)&context_id;

	register u32 r2 asm("r2") = arg1;



	asm volatile(

			__asmeq("%0", "r0")

			__asmeq("%1", "r0")

			__asmeq("%2", "r1")

			__asmeq("%3", "r2")

#ifdef REQUIRES_SEC

			".arch_extension sec\n"

#endif

			"smc    #0      @ switch to secure world\n"

			: "=r" (r0)

			: "r" (r0), "r" (r1), "r" (r2)

			: "r3", "r12");

	return r0;

	return res.a0;

}



/**
@@ -273,26 +250,12 @@ static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1) 
static s32 qcom_scm_call_atomic2(u32 svc, u32 cmd, u32 arg1, u32 arg2)

{

	int context_id;

	struct arm_smccc_res res;



	arm_smccc_smc(LEGACY_ATOMIC_ID(svc, cmd, 2), (unsigned long)&context_id,

		      arg1, arg2, 0, 0, 0, 0, &res);



	register u32 r0 asm("r0") = LEGACY_ATOMIC_ID(svc, cmd, 2);

	register u32 r1 asm("r1") = (u32)&context_id;

	register u32 r2 asm("r2") = arg1;

	register u32 r3 asm("r3") = arg2;



	asm volatile(

			__asmeq("%0", "r0")

			__asmeq("%1", "r0")

			__asmeq("%2", "r1")

			__asmeq("%3", "r2")

			__asmeq("%4", "r3")

#ifdef REQUIRES_SEC

			".arch_extension sec\n"

#endif

			"smc    #0      @ switch to secure world\n"

			: "=r" (r0)

			: "r" (r0), "r" (r1), "r" (r2), "r" (r3)

			: "r12");

	return r0;

	return res.a0;

}



/**