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Commit fdfec172 authored by Michael Chan's avatar Michael Chan Committed by David S. Miller
Browse files

[TG3]: consolidate all DMA water mark settings 



Consolidate all DMA watermark settings for standard and jumbo frames on
all chips in tg3_init_bufmgr_config() and add new settings for 5780.

Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 7e72aad4

drivers/net/tg3.c

+30 −23
Original line number Diff line number Diff line
@@ -9826,6 +9826,21 @@ static void __devinit tg3_init_link_config(struct tg3 *tp) 


static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)

{

	if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {

		tp->bufmgr_config.mbuf_read_dma_low_water =

			DEFAULT_MB_RDMA_LOW_WATER_5705;

		tp->bufmgr_config.mbuf_mac_rx_low_water =

			DEFAULT_MB_MACRX_LOW_WATER_5705;

		tp->bufmgr_config.mbuf_high_water =

			DEFAULT_MB_HIGH_WATER_5705;



		tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =

			DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;

		tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =

			DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;

		tp->bufmgr_config.mbuf_high_water_jumbo =

			DEFAULT_MB_HIGH_WATER_JUMBO_5780;

	} else {

		tp->bufmgr_config.mbuf_read_dma_low_water =

			DEFAULT_MB_RDMA_LOW_WATER;

		tp->bufmgr_config.mbuf_mac_rx_low_water =
@@ -9839,6 +9854,7 @@ static void __devinit tg3_init_bufmgr_config(struct tg3 *tp) 
			DEFAULT_MB_MACRX_LOW_WATER_JUMBO;

		tp->bufmgr_config.mbuf_high_water_jumbo =

			DEFAULT_MB_HIGH_WATER_JUMBO;

	}



	tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;

	tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
@@ -10052,8 +10068,6 @@ static int __devinit tg3_init_one(struct pci_dev *pdev, 


	tg3_init_link_config(tp);



	tg3_init_bufmgr_config(tp);



	tp->rx_pending = TG3_DEF_RX_RING_PENDING;

	tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;

	tp->tx_pending = TG3_DEF_TX_RING_PENDING;
@@ -10082,14 +10096,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev, 
		goto err_out_iounmap;

	}



	if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {

		tp->bufmgr_config.mbuf_read_dma_low_water =

			DEFAULT_MB_RDMA_LOW_WATER_5705;

		tp->bufmgr_config.mbuf_mac_rx_low_water =

			DEFAULT_MB_MACRX_LOW_WATER_5705;

		tp->bufmgr_config.mbuf_high_water =

			DEFAULT_MB_HIGH_WATER_5705;

	}

	tg3_init_bufmgr_config(tp);



#if TG3_TSO_SUPPORT != 0

	if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {

drivers/net/tg3.h

+3 −0
Original line number Diff line number Diff line
@@ -985,14 +985,17 @@ 
#define  DEFAULT_MB_RDMA_LOW_WATER	 0x00000050

#define  DEFAULT_MB_RDMA_LOW_WATER_5705	 0x00000000

#define  DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130

#define  DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000

#define BUFMGR_MB_MACRX_LOW_WATER	0x00004414

#define  DEFAULT_MB_MACRX_LOW_WATER	  0x00000020

#define  DEFAULT_MB_MACRX_LOW_WATER_5705  0x00000010

#define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098

#define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b

#define BUFMGR_MB_HIGH_WATER		0x00004418

#define  DEFAULT_MB_HIGH_WATER		 0x00000060

#define  DEFAULT_MB_HIGH_WATER_5705	 0x00000060

#define  DEFAULT_MB_HIGH_WATER_JUMBO	 0x0000017c

#define  DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096

#define BUFMGR_RX_MB_ALLOC_REQ		0x0000441c

#define  BUFMGR_MB_ALLOC_BIT		 0x10000000

#define BUFMGR_RX_MB_ALLOC_RESP		0x00004420