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Commit fdbcc04d authored by Lucas Stach's avatar Lucas Stach Committed by Shawn Guo
Browse files

arm64: dts: imx8mq: add GPC power domains 



This adds support for the power domain controller found on the
i.MX8MQ SoC.

Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent a0e046e6

arch/arm64/boot/dts/freescale/imx8mq.dtsi

+70 −0
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ 
 */



#include <dt-bindings/clock/imx8mq-clock.h>

#include <dt-bindings/power/imx8mq-power.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "imx8mq-pinfunc.h"
@@ -252,6 +253,75 @@ 
				              "clk_ext1", "clk_ext2",

				              "clk_ext3", "clk_ext4";

			};



			gpc: gpc@303a0000 {

				compatible = "fsl,imx8mq-gpc";

				reg = <0x303a0000 0x10000>;



				pgc {

					#address-cells = <1>;

					#size-cells = <0>;



					pgc_mipi: power-domain@0 {

						#power-domain-cells = <0>;

						reg = <IMX8M_POWER_DOMAIN_MIPI>;

					};



					pgc_pcie1: power-domain@1 {

						#power-domain-cells = <0>;

						reg = <IMX8M_POWER_DOMAIN_PCIE1>;

					};



					pgc_otg1: power-domain@2 {

						#power-domain-cells = <0>;

						reg = <IMX8M_POWER_DOMAIN_USB_OTG1>;

					};



					pgc_otg2: power-domain@3 {

						#power-domain-cells = <0>;

						reg = <IMX8M_POWER_DOMAIN_USB_OTG2>;

					};



					pgc_ddr1: power-domain@4 {

						#power-domain-cells = <0>;

						reg = <IMX8M_POWER_DOMAIN_DDR1>;

					};



					pgc_gpu: power-domain@5 {

						#power-domain-cells = <0>;

						reg = <IMX8M_POWER_DOMAIN_GPU>;

						clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,

						         <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,

							 <&clk IMX8MQ_CLK_GPU_AXI>,

						         <&clk IMX8MQ_CLK_GPU_AHB>;

					};



					pgc_vpu: power-domain@6 {

						#power-domain-cells = <0>;

						reg = <IMX8M_POWER_DOMAIN_VPU>;

					};



					pgc_disp: power-domain@7 {

						#power-domain-cells = <0>;

						reg = <IMX8M_POWER_DOMAIN_DISP>;

					};



					pgc_mipi_csi1: power-domain@8 {

						#power-domain-cells = <0>;

						reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>;

					};



					pgc_mipi_csi2: power-domain@9 {

						#power-domain-cells = <0>;

						reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>;

					};



					pgc_pcie2: power-domain@a {

						#power-domain-cells = <0>;

						reg = <IMX8M_POWER_DOMAIN_PCIE2>;

					};

				};

			};

		};



		bus@30400000 { /* AIPS2 */