Merge tag 'LA.UM.9.14.r1-20700-LAHAINA.QSSI13.0' of... (fd6c2819) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/staging/fw-api/fw/htt.h

+6 −0

Original line number	Diff line number	Diff line
		@@ -754,6 +754,12 @@ typedef enum {
		HTT_STATS_TX_PDEV_PPDU_DUR_TAG = 162, /* htt_tx_pdev_ppdu_dur_stats_tlv */
		HTT_STATS_RX_PDEV_PPDU_DUR_TAG = 163, /* htt_rx_pdev_ppdu_dur_stats_tlv */
		HTT_STATS_ODD_PDEV_MANDATORY_TAG = 164, /* htt_odd_mandatory_pdev_stats_tlv */
		HTT_STATS_PDEV_SCHED_ALGO_OFDMA_STATS_TAG = 165, /* htt_pdev_sched_algo_ofdma_stats_tlv */
		HTT_DBG_ODD_MANDATORY_MUMIMO_TAG = 166, /* htt_odd_mandatory_mumimo_pdev_stats_tlv */
		HTT_DBG_ODD_MANDATORY_MUOFDMA_TAG = 167, /* htt_odd_mandatory_muofdma_pdev_stats_tlv */
		HTT_STATS_LATENCY_PROF_CAL_STATS_TAG = 168, /* htt_latency_prof_cal_stats_tlv */
		HTT_STATS_TX_PDEV_MUEDCA_PARAMS_STATS_TAG = 169, /* htt_tx_pdev_muedca_params_stats_tlv_v */
		HTT_STATS_PDEV_BW_MGR_STATS_TAG = 170, /* htt_pdev_bw_mgr_stats_tlv */


		HTT_STATS_MAX_TAG,

drivers/staging/fw-api/fw/htt_stats.h

+370 −6

Original line number	Diff line number	Diff line
		@@ -348,7 +348,7 @@ enum htt_dbg_ext_stats_type {
		*/
		HTT_DBG_EXT_STATS_PDEV_TX_RATE_TXBF = 31,

		/* HTT_DBG_EXT_STATS_TXBF_OFDMA
		/** HTT_DBG_EXT_STATS_TXBF_OFDMA
		*/
		HTT_DBG_EXT_STATS_TXBF_OFDMA = 32,

		@@ -422,7 +422,7 @@ enum htt_dbg_ext_stats_type {
		*/
		HTT_DBG_EXT_RX_RING_STATS = 42,

		/* HTT_STRM_GEN_MPDUS_STATS, HTT_STRM_GEN_MPDUS_DETAILS_STATS
		/** HTT_STRM_GEN_MPDUS_STATS, HTT_STRM_GEN_MPDUS_DETAILS_STATS
		* PARAMS:
		* - No params
		* RESP MSG: HTT_T2H STREAMING_STATS_IND (not EXT_STATS_CONF)
		@@ -451,7 +451,7 @@ enum htt_dbg_ext_stats_type {
		*/
		HTT_DBG_PDEV_PUNCTURE_STATS = 46,

		/* HTT_DBG_EXT_STATS_ML_PEERS_INFO
		/** HTT_DBG_EXT_STATS_ML_PEERS_INFO
		* PARAMS:
		* - param 0:
		* Bit 0 -> HTT_ML_PEER_DETAILS_TLV always enabled by default
		@@ -463,7 +463,7 @@ enum htt_dbg_ext_stats_type {
		*/
		HTT_DBG_EXT_STATS_ML_PEERS_INFO = 47,

		/* HTT_DBG_ODD_MANDATORY_STATS
		/** HTT_DBG_ODD_MANDATORY_STATS
		* params:
		* None
		* Response MSG:
		@@ -471,6 +471,45 @@ enum htt_dbg_ext_stats_type {
		*/
		HTT_DBG_ODD_MANDATORY_STATS = 48,

		/** HTT_DBG_PDEV_SCHED_ALGO_STATS
		* PARAMS:
		* - No Params
		* RESP MSG:
		* - htt_pdev_sched_algo_ofdma_stats_tlv
		*/
		HTT_DBG_PDEV_SCHED_ALGO_STATS = 49,

		/** HTT_DBG_ODD_MANDATORY_MUMIMO_STATS
		* params:
		* None
		* Response MSG:
		* htt_odd_mandatory_mumimo_pdev_stats_tlv
		*/
		HTT_DBG_ODD_MANDATORY_MUMIMO_STATS = 50,
		/** HTT_DBG_ODD_MANDATORY_MUOFDMA_STATS
		* params:
		* None
		* Response MSG:
		* htt_odd_mandatory_muofdma_pdev_stats_tlv
		*/
		HTT_DBG_ODD_MANDATORY_MUOFDMA_STATS = 51,

		/** HTT_DBG_EXT_PHY_PROF_CAL_STATS
		* params:
		* None
		* Response MSG:
		* htt_latency_prof_cal_stats_tlv
		*/
		HTT_DBG_EXT_PHY_PROF_CAL_STATS = 52,

		/** HTT_DBG_EXT_STATS_PDEV_BW_MGR
		* PARAMS:
		* - No Params
		* RESP MSG:
		* - htt_pdev_bw_mgr_stats_t
		*/
		HTT_DBG_EXT_STATS_PDEV_BW_MGR = 53,


		/* keep this last */
		HTT_DBG_NUM_EXT_STATS = 256,
		@@ -861,6 +900,8 @@ typedef struct {
		A_UINT32 num_dyn_mimo_ps_dlmumimo_sequences;
		/** Num of times su bf sequences are denylisted */
		A_UINT32 num_su_txbf_denylisted;
		/ pdev uptime in microseconds /
		A_UINT32 pdev_up_time_us;
		} htt_tx_pdev_stats_cmn_tlv;

		#define HTT_TX_PDEV_STATS_URRN_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems))
		@@ -891,6 +932,20 @@ typedef struct {
		A_UINT32 phy_errs[1]; /* HTT_TX_PDEV_MAX_PHY_ERR_STATS */
		} htt_tx_pdev_stats_phy_err_tlv_v;

		/*
		* Each array in the below struct has 16 elements, to cover the 16 possible
		* values for the CW and AIFS parameters. Each element within the array
		* stores the counter indicating how many transmissions have occurred with
		* that particular value for the MU EDCA parameter in question.
		*/
		#define HTT_STATS_MUEDCA_VALUE_MAX 16
		typedef struct {
		htt_tlv_hdr_t tlv_hdr;
		A_UINT32 aifs[HTT_NUM_AC_WMM][HTT_STATS_MUEDCA_VALUE_MAX];
		A_UINT32 cw_min[HTT_NUM_AC_WMM][HTT_STATS_MUEDCA_VALUE_MAX];
		A_UINT32 cw_max[HTT_NUM_AC_WMM][HTT_STATS_MUEDCA_VALUE_MAX];
		} htt_tx_pdev_muedca_params_stats_tlv_v;

		#define HTT_TX_PDEV_SIFS_BURST_HIST_STATS 10
		#define HTT_TX_PDEV_STATS_SIFS_HIST_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems))
		/* NOTE: Variable length TLV, use length spec to infer array size */
		@@ -1532,7 +1587,9 @@ typedef struct {
		mesh_sta : 1,
		mec : 1,
		intra_bss : 1,
		reserved : 16;
		chip_id : 2,
		ml_peer_id : 13,
		reserved : 1;
		} htt_ast_entry_tlv;

		typedef enum {
		@@ -1642,6 +1699,7 @@ typedef struct _htt_tx_peer_rate_stats_tlv {
		A_UINT32 tx_stbc_ext[HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS];
		A_UINT32 tx_gi_ext[HTT_TX_PEER_STATS_NUM_GI_COUNTERS][HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS];
		A_UINT32 reduced_tx_bw[HTT_TX_PEER_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_PEER_STATS_NUM_BW_COUNTERS];
		A_UINT32 tx_bw_320mhz;
		} htt_tx_peer_rate_stats_tlv;

		#define HTT_RX_PEER_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */
		@@ -3600,7 +3658,7 @@ typedef struct {

		/* == TQM STATS == */

		#define HTT_TX_TQM_MAX_GEN_MPDU_END_REASON 16
		#define HTT_TX_TQM_MAX_GEN_MPDU_END_REASON 17
		#define HTT_TX_TQM_MAX_LIST_MPDU_END_REASON 16
		#define HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS 16

		@@ -4886,6 +4944,8 @@ typedef struct {
		htt_tlv_hdr_t tlv_hdr;
		/ Tx PPDU duration histogram /
		A_UINT32 tx_ppdu_dur_hist[HTT_PDEV_STATS_PPDU_DUR_HIST_BINS];
		A_UINT32 tx_success_time_us;
		A_UINT32 tx_fail_time_us;
		} htt_tx_pdev_ppdu_dur_stats_tlv;

		/* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_TX_RATE
		@@ -6315,6 +6375,14 @@ typedef struct {
		A_UINT32 cv_buf_received;
		/** total times CV bufs fed back to the IPC ring */
		A_UINT32 cv_buf_fed_back;
		/* Total times CV query happened for IBF case */
		A_UINT32 cv_total_query_ibf;
		/* A valid CV has been found for IBF case */
		A_UINT32 cv_found_ibf;
		/* A valid CV has not been found for IBF case */
		A_UINT32 cv_not_found_ibf;
		/* Expired CV found during query for IBF case */
		A_UINT32 cv_expired_during_query_ibf;
		} htt_tx_sounding_stats_tlv;

		/* STATS_TYPE : HTT_DBG_EXT_STATS_TX_SOUNDING_INFO
		@@ -6753,6 +6821,7 @@ typedef enum {
		HTT_STATS_RC_MODE_DLSU = 0,
		HTT_STATS_RC_MODE_DLMUMIMO = 1,
		HTT_STATS_RC_MODE_DLOFDMA = 2,
		HTT_STATS_RC_MODE_ULMUMIMO = 3,
		} htt_stats_rc_mode;

		typedef struct {
		@@ -7697,6 +7766,73 @@ typedef struct {
		A_UINT32 num_subbands_used_cnt[HTT_PUNCTURE_STATS_MAX_SUBBAND_COUNT];
		} htt_pdev_puncture_stats_tlv;

		enum {
		HTT_STATS_CAL_PROF_COLD_BOOT = 0,
		HTT_STATS_CAL_PROF_FULL_CHAN_SWITCH = 1,
		HTT_STATS_CAL_PROF_SCAN_CHAN_SWITCH = 2,
		HTT_STATS_CAL_PROF_DPD_SPLIT_CAL = 3,

		HTT_STATS_MAX_PROF_CAL = 4,
		};

		#define HTT_STATS_MAX_CAL_IDX_CNT 8
		typedef struct {

		htt_tlv_hdr_t tlv_hdr;

		A_UINT8 latency_prof_name[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_PROF_STATS_NAME_LEN];

		/** To verify whether prof cal is enabled or not */
		A_UINT32 enable;

		/** current pdev_id */
		A_UINT32 pdev_id;

		/** The cnt is incremented when each time the calindex takes place */
		A_UINT32 cnt[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT];

		/** Minimum time taken to complete the calibration - in us */
		A_UINT32 min[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT];

		/** Maximum time taken to complete the calibration -in us */
		A_UINT32 max[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT];

		/** Time taken by the cal for its final time execution - in us */
		A_UINT32 last[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT];

		/** Total time taken - in us */
		A_UINT32 tot[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT];

		/** hist_intvl - by default will be set to 2000 us */
		A_UINT32 hist_intvl[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT];

		/**
		* If last is less than hist_intvl, then hist[0]++,
		* If last is less than hist_intvl << 1, then hist[1]++,
		* otherwise hist[2]++.
		*/
		A_UINT32 hist[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT][HTT_INTERRUPTS_LATENCY_PROFILE_MAX_HIST];

		/** Pf_last will log the current no of page faults */
		A_UINT32 pf_last[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT];

		/** Sum of all page faults happened */
		A_UINT32 pf_tot[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT];

		/** If pf_last > pf_max then pf_max = pf_last */
		A_UINT32 pf_max[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT];

		/**
		* For each cal profile, only certain no of cal indices were invoked,
		* this member will store what all the indices got invoked per each
		* cal profile
		*/
		A_UINT32 enabledCalIdx[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT];

		/** No of indices invoked per each cal profile */
		A_UINT32 CalCnt[HTT_STATS_MAX_PROF_CAL];
		} htt_latency_prof_cal_stats_tlv;

		#define HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_M 0x0000003F
		#define HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_S 0
		#define HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_M 0x00000FC0
		@@ -8250,5 +8386,233 @@ typedef struct {
		A_UINT32 rts_success;
		} htt_odd_mandatory_pdev_stats_tlv;

		typedef struct _htt_odd_mandatory_mumimo_pdev_stats_tlv {
		htt_tlv_hdr_t tlv_hdr;
		A_UINT32 ac_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
		A_UINT32 ax_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
		A_UINT32 ac_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
		A_UINT32 ax_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
		A_UINT32 ac_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
		A_UINT32 ax_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
		A_UINT32 ul_mumimo_rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
		A_UINT32 ul_mumimo_rx_nss[HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS];
		A_UINT32 ul_mumimo_rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS];
		A_UINT32 rx_ulmumimo_mpdu_fail[HTT_RX_PDEV_MAX_OFDMA_NUM_USER];
		A_UINT32 rx_ulmumimo_mpdu_ok[HTT_RX_PDEV_MAX_OFDMA_NUM_USER];
		A_UINT32 rx_ulmumimo_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER];
		} htt_odd_mandatory_mumimo_pdev_stats_tlv;

		typedef struct _htt_odd_mandatory_muofdma_pdev_stats_tlv {
		htt_tlv_hdr_t tlv_hdr;
		A_UINT32 mu_ofdma_seq_posted;
		A_UINT32 ul_mu_ofdma_seq_posted;
		A_UINT32 ofdma_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS + HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS + HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS];
		A_UINT32 ofdma_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
		A_UINT32 ofdma_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
		A_UINT32 ofdma_tx_ldpc;
		A_UINT32 ul_ofdma_rx_ldpc;
		A_UINT32 ul_ofdma_rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS + HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS + HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS];
		A_UINT32 ul_ofdma_rx_nss[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS];
		A_UINT32 ul_ofdma_rx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
		A_UINT32 rx_ulofdma_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER];
		A_UINT32 rx_ulofdma_mpdu_ok[HTT_RX_PDEV_MAX_OFDMA_NUM_USER];
		A_UINT32 rx_ulofdma_mpdu_fail[HTT_RX_PDEV_MAX_OFDMA_NUM_USER];
		A_UINT32 ax_mu_brp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
		A_UINT32 be_mu_brp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
		A_UINT32 ofdma_tx_ru_size[HTT_TX_PDEV_STATS_NUM_AX_RU_SIZE_COUNTERS];
		} htt_odd_mandatory_muofdma_pdev_stats_tlv;


		#define HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID_M 0x000000ff
		#define HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID_S 0

		#define HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID_GET(_var) \
		(((_var) & HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID_M) >> \
		HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID_S)

		#define HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID, _val); \
		((_var) \|= ((_val) << HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID_S)); \
		} while (0)

		typedef struct {
		htt_tlv_hdr_t tlv_hdr;
		/**
		* BIT [ 7 : 0] :- mac_id
		* BIT [31 : 8] :- reserved
		*/
		union {
		struct {
		A_UINT32 mac_id: 8,
		reserved: 24;
		};
		A_UINT32 mac_id__word;
		};

		/** Num of instances where rate based DL OFDMA status = ENABLED */
		A_UINT32 rate_based_dlofdma_enabled_count[HTT_NUM_AC_WMM];
		/** Num of instances where rate based DL OFDMA status = DISABLED */
		A_UINT32 rate_based_dlofdma_disabled_count[HTT_NUM_AC_WMM];
		/** Num of instances where rate based DL OFDMA status = PROBING */
		A_UINT32 rate_based_dlofdma_probing_count[HTT_NUM_AC_WMM];
		/** Num of instances where rate based DL OFDMA status = MONITORING */
		A_UINT32 rate_based_dlofdma_monitoring_count[HTT_NUM_AC_WMM];
		/** Num of instances where avg. channel access latency based DL OFDMA status = ENABLED */
		A_UINT32 chan_acc_lat_based_dlofdma_enabled_count[HTT_NUM_AC_WMM];
		/** Num of instances where avg. channel access latency based DL OFDMA status = DISABLED */
		A_UINT32 chan_acc_lat_based_dlofdma_disabled_count[HTT_NUM_AC_WMM];
		/** Num of instances where avg. channel access latency based DL OFDMA status = MONITORING */
		A_UINT32 chan_acc_lat_based_dlofdma_monitoring_count[HTT_NUM_AC_WMM];
		/** Num of instances where dl ofdma is disabled due to ru allocation failure */
		A_UINT32 downgrade_to_dl_su_ru_alloc_fail[HTT_NUM_AC_WMM];
		/** Num of instances where dl ofdma is disabled because we have only one user in candidate list */
		A_UINT32 candidate_list_single_user_disable_ofdma[HTT_NUM_AC_WMM];
		/** Num of instances where ul is chosen over dl based on qos weight not specific to OFDMA */
		A_UINT32 dl_cand_list_dropped_high_ul_qos_weight[HTT_NUM_AC_WMM];
		/** Num of instances where dl ofdma is disabled due to pipelining */
		A_UINT32 ax_dlofdma_disabled_due_to_pipelining[HTT_NUM_AC_WMM];
		/** Num of instances where dl ofdma is disabled as the tid is su only eligible */
		A_UINT32 dlofdma_disabled_su_only_eligible[HTT_NUM_AC_WMM];
		/** Num of instances where dl ofdma is disabled because there are no mpdus tried consecutively */
		A_UINT32 dlofdma_disabled_consec_no_mpdus_tried[HTT_NUM_AC_WMM];
		/** Num of instances where dl ofdma is disabled because there are consecutive mpdu failure */
		A_UINT32 dlofdma_disabled_consec_no_mpdus_success[HTT_NUM_AC_WMM];
		} htt_pdev_sched_algo_ofdma_stats_tlv;

		/======= Bandwidth Manager stats ====================/

		#define HTT_BW_MGR_STATS_MAC_ID_M 0x000000ff
		#define HTT_BW_MGR_STATS_MAC_ID_S 0

		#define HTT_BW_MGR_STATS_PRI20_IDX_M 0x0000ff00
		#define HTT_BW_MGR_STATS_PRI20_IDX_S 8

		#define HTT_BW_MGR_STATS_PRI20_FREQ_M 0xffff0000
		#define HTT_BW_MGR_STATS_PRI20_FREQ_S 16

		#define HTT_BW_MGR_STATS_CENTER_FREQ1_M 0x0000ffff
		#define HTT_BW_MGR_STATS_CENTER_FREQ1_S 0

		#define HTT_BW_MGR_STATS_CENTER_FREQ2_M 0xffff0000
		#define HTT_BW_MGR_STATS_CENTER_FREQ2_S 16

		#define HTT_BW_MGR_STATS_CHAN_PHY_MODE_M 0x000000ff
		#define HTT_BW_MGR_STATS_CHAN_PHY_MODE_S 0

		#define HTT_BW_MGR_STATS_STATIC_PATTERN_M 0x00ffff00
		#define HTT_BW_MGR_STATS_STATIC_PATTERN_S 8

		#define HTT_BW_MGR_STATS_MAC_ID_GET(_var) \
		(((_var) & HTT_BW_MGR_STATS_MAC_ID_M) >> \
		HTT_BW_MGR_STATS_MAC_ID_S)

		#define HTT_BW_MGR_STATS_MAC_ID_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_MAC_ID, _val); \
		((_var) \|= ((_val) << HTT_BW_MGR_STATS_MAC_ID_S)); \
		} while (0)


		#define HTT_BW_MGR_STATS_PRI20_IDX_GET(_var) \
		(((_var) & HTT_BW_MGR_STATS_PRI20_IDX_M) >> \
		HTT_BW_MGR_STATS_PRI20_IDX_S)

		#define HTT_BW_MGR_STATS_PRI20_IDX_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_PRI20_IDX, _val); \
		((_var) \|= ((_val) << HTT_BW_MGR_STATS_PRI20_IDX_S)); \
		} while (0)


		#define HTT_BW_MGR_STATS_PRI20_FREQ_GET(_var) \
		(((_var) & HTT_BW_MGR_STATS_PRI20_FREQ_M) >> \
		HTT_BW_MGR_STATS_PRI20_FREQ_S)

		#define HTT_BW_MGR_STATS_PRI20_FREQ_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_PRI20_FREQ, _val); \
		((_var) \|= ((_val) << HTT_BW_MGR_STATS_PRI20_FREQ_S)); \
		} while (0)


		#define HTT_BW_MGR_STATS_CENTER_FREQ1_GET(_var) \
		(((_var) & HTT_BW_MGR_STATS_CENTER_FREQ1_M) >> \
		HTT_BW_MGR_STATS_CENTER_FREQ1_S)

		#define HTT_BW_MGR_STATS_CENTER_FREQ1_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_CENTER_FREQ1, _val); \
		((_var) \|= ((_val) << HTT_BW_MGR_STATS_CENTER_FREQ1_S)); \
		} while (0)


		#define HTT_BW_MGR_STATS_CENTER_FREQ2_GET(_var) \
		(((_var) & HTT_BW_MGR_STATS_CENTER_FREQ2_M) >> \
		HTT_BW_MGR_STATS_CENTER_FREQ2_S)

		#define HTT_BW_MGR_STATS_CENTER_FREQ2_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_CENTER_FREQ2, _val); \
		((_var) \|= ((_val) << HTT_BW_MGR_STATS_CENTER_FREQ2_S)); \
		} while (0)


		#define HTT_BW_MGR_STATS_CHAN_PHY_MODE_GET(_var) \
		(((_var) & HTT_BW_MGR_STATS_CHAN_PHY_MODE_M) >> \
		HTT_BW_MGR_STATS_CHAN_PHY_MODE_S)

		#define HTT_BW_MGR_STATS_CHAN_PHY_MODE_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_CHAN_PHY_MODE, _val); \
		((_var) \|= ((_val) << HTT_BW_MGR_STATS_CHAN_PHY_MODE_S)); \
		} while (0)


		#define HTT_BW_MGR_STATS_STATIC_PATTERN_GET(_var) \
		(((_var) & HTT_BW_MGR_STATS_STATIC_PATTERN_M) >> \
		HTT_BW_MGR_STATS_STATIC_PATTERN_S)

		#define HTT_BW_MGR_STATS_STATIC_PATTERN_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_STATIC_PATTERN, _val); \
		((_var) \|= ((_val) << HTT_BW_MGR_STATS_STATIC_PATTERN_S)); \
		} while (0)


		typedef struct {
		htt_tlv_hdr_t tlv_hdr;

		/* BIT [ 7 : 0] :- mac_id
		* BIT [ 15 : 8] :- pri20_index
		* BIT [ 31 : 16] :- pri20_freq in Mhz
		*/
		A_UINT32 mac_id__pri20_idx__freq;

		/* BIT [ 15 : 0] :- centre_freq1
		* BIT [ 31 : 16] :- centre_freq2
		*/
		A_UINT32 centre_freq1__freq2;

		/* BIT [ 7 : 0] :- channel_phy_mode
		* BIT [ 23 : 8] :- static_pattern
		*/
		A_UINT32 phy_mode__static_pattern;

		} htt_pdev_bw_mgr_stats_tlv;


		/* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_BW_MGR
		* TLV_TAGS:
		* - HTT_STATS_PDEV_BW_MGR_STATS_TAG
		*/
		/* NOTE:
		* This structure is for documentation, and cannot be safely used directly.
		* Instead, use the constituent TLV structures to fill/parse.
		*/
		typedef struct {
		htt_pdev_bw_mgr_stats_tlv bw_mgr_tlv;
		} htt_pdev_bw_mgr_stats_t;


		#endif /* __HTT_STATS_H__ */

drivers/staging/fw-api/fw/wlan_module_ids.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -138,6 +138,8 @@ typedef enum {

		WLAN_MODULE_T2LM, /* 0x64 */
		WLAN_MODULE_HEALTH_MON, /* 0x65 */
		WLAN_MODULE_XGAP, /* 0x66 */


		WLAN_MODULE_ID_MAX,
		WLAN_MODULE_ID_INVALID = WLAN_MODULE_ID_MAX,

drivers/staging/fw-api/fw/wlanfw_health_mon.h

0 → 100644

+251 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/staging/fw-api/fw/wmi_services.h

+14 −7

Original line number	Diff line number	Diff line
		@@ -594,6 +594,13 @@ typedef enum {
		WMI_SERVICE_COAP_OFFLOAD_SUPPORT = 341, /* FW supports CoAP (the Constrained Application Protocol) offload */
		WMI_SERVICE_TDLS_WIDEBAND_SUPPORT = 342, /* FW supports Wideband TDLS */
		WMI_SERVICE_FEATURE_SET_EVENT_SUPPORT = 343, /* FW supports sending of supported feature set event during init time */
		WMI_SERVICE_HALPHY_CTRL_PATH_STATS = 344, /* HALPHY STATS through control path */
		WMI_SERVICE_PEER_CHWIDTH_PUNCTURE_BITMAP_SUPPORT = 345, /* FW supports puncture bitmap change with channel width switch */
		WMI_SERVICE_BANG_RADAR_320_SUPPORT = 346, /* Host to send frequency offset for bang radar in extended field for 320M support */
		WMI_SERVICE_XGAP_SUPPORT = 347, /* FW support for XGAP */
		WMI_SERVICE_OBSS_PER_PACKET_SR_SUPPORT = 348, /* Spatial Reuse support for per PPDU setting */
		WMI_SERVICE_MULTIPLE_VDEV_RESTART_BITMAP_SUPPORT = 349, /* Extended Multiple VDEV Restart with Bitmap Support */


		WMI_MAX_EXT2_SERVICE

		@@ -627,15 +634,15 @@ typedef enum {
		*/
		#define WMI_SERVICE_ENABLE(pwmi_svc_bmap,svc_id) \
		( (pwmi_svc_bmap)[(svc_id)/(sizeof(A_UINT32))] \|= \
		(1 << ((svc_id)%(sizeof(A_UINT32)))) )
		((A_UINT32) 1 << ((svc_id)%(sizeof(A_UINT32)))) )

		#define WMI_SERVICE_DISABLE(pwmi_svc_bmap,svc_id) \
		( (pwmi_svc_bmap)[(svc_id)/(sizeof(A_UINT32))] &= \
		( ~(1 << ((svc_id)%(sizeof(A_UINT32)))) ) )
		( ~((A_UINT32) 1 << ((svc_id)%(sizeof(A_UINT32)))) ) )

		#define WMI_SERVICE_IS_ENABLED(pwmi_svc_bmap,svc_id) \
		( ((pwmi_svc_bmap)[(svc_id)/(sizeof(A_UINT32))] & \
		(1 << ((svc_id)%(sizeof(A_UINT32)))) ) != 0)
		((A_UINT32) 1 << ((svc_id)%(sizeof(A_UINT32)))) ) != 0)


		#define WMI_SERVICE_EXT_ENABLE(pwmi_svc_bmap, pwmi_svc_ext_bmap, svc_id) \
		@@ -645,7 +652,7 @@ typedef enum {
		} else { \
		int word = ((svc_id) - WMI_MAX_SERVICE) / 32; \
		int bit = (svc_id) & 0x1f; /* svc_id mod 32 */ \
		(pwmi_svc_ext_bmap)[word] \|= (1 << bit); \
		(pwmi_svc_ext_bmap)[word] \|= ((A_UINT32) 1 << bit); \
		} \
		} while (0)

		@@ -656,7 +663,7 @@ typedef enum {
		} else { \
		int word = ((svc_id) - WMI_MAX_SERVICE) / 32; \
		int bit = (svc_id) & 0x1f; /* svc_id mod 32 */ \
		(pwmi_svc_ext_bmap)[word] &= ~(1 << bit); \
		(pwmi_svc_ext_bmap)[word] &= ~((A_UINT32) 1 << bit); \
		} \
		} while (0)

		@@ -680,7 +687,7 @@ typedef enum {
		} else { \
		int word = ((svc_id) - WMI_MAX_EXT_SERVICE) / 32; \
		int bit = (svc_id) & 0x1f; /* svc_id mod 32 */ \
		(pwmi_svc_ext2_bmap)[word] \|= (1 << bit); \
		(pwmi_svc_ext2_bmap)[word] \|= ((A_UINT32) 1 << bit); \
		} \
		} while (0)

		@@ -694,7 +701,7 @@ typedef enum {
		} else { \
		int word = ((svc_id) - WMI_MAX_EXT_SERVICE) / 32; \
		int bit = (svc_id) & 0x1f; /* svc_id mod 32 */ \
		(pwmi_svc_ext2_bmap)[word] &= ~(1 << bit); \
		(pwmi_svc_ext2_bmap)[word] &= ~((A_UINT32) 1 << bit); \
		} \
		} while (0)