Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit fd37ce34 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net 

Pull networking update from David S. Miller:
 "I think Eric Dumazet and I have dealt with all of the known routing
  cache removal fallout.  Some other minor fixes all around.

  1) Fix RCU of cached routes, particular of output routes which require
     liberation via call_rcu() instead of call_rcu_bh().  From Eric
     Dumazet.

  2) Make sure we purge net device references in cached routes properly.

  3) TG3 driver bug fixes from Michael Chan.

  4) Fix reported 'expires' value in ipv6 routes, from Li Wei.

  5) TUN driver ioctl leaks kernel bytes to userspace, from Mathias
     Krause."

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net: (22 commits)
  ipv4: Properly purge netdev references on uncached routes.
  ipv4: Cache routes in nexthop exception entries.
  ipv4: percpu nh_rth_output cache
  ipv4: Restore old dst_free() behavior.
  bridge: make port attributes const
  ipv4: remove rt_cache_rebuild_count
  net: ipv4: fix RCU races on dst refcounts
  net: TCP early demux cleanup
  tun: Fix formatting.
  net/tun: fix ioctl() based info leaks
  tg3: Update version to 3.124
  tg3: Fix race condition in tg3_get_stats64()
  tg3: Add New 5719 Read DMA workaround
  tg3: Fix Read DMA workaround for 5719 A0.
  tg3: Request APE_LOCK_PHY before PHY access
  ipv6: fix incorrect route 'expires' value passed to userspace
  mISDN: Bugfix only few bytes are transfered on a connection
  seeq: use PTR_RET at init_module of driver
  bnx2x: remove cast around the kmalloc in bnx2x_prev_mark_path
  ipv4: clean up put_child
  ...
parents 4b24ff71 caacf05e

Documentation/networking/ip-sysctl.txt

+0 −6
Original line number Diff line number Diff line
@@ -48,12 +48,6 @@ min_adv_mss - INTEGER 
	The advertised MSS depends on the first hop route MTU, but will

	never be lower than this setting.



rt_cache_rebuild_count - INTEGER

	The per net-namespace route cache emergency rebuild threshold.

	Any net-namespace having its route cache rebuilt due to

	a hash bucket chain being too long more than this many times

	will have its route caching disabled



IP Fragmentation:



ipfrag_high_thresh - INTEGER

drivers/isdn/hardware/mISDN/avmfritz.c

+4 −3
Original line number Diff line number Diff line
@@ -449,7 +449,8 @@ hdlc_fill_fifo(struct bchannel *bch) 
{

	struct fritzcard *fc = bch->hw;

	struct hdlc_hw *hdlc;

	int count, fs, cnt = 0, idx, fillempty = 0;

	int count, fs, cnt = 0, idx;

	bool fillempty = false;

	u8 *p;

	u32 *ptr, val, addr;
@@ -462,7 +463,7 @@ hdlc_fill_fifo(struct bchannel *bch) 
			return;

		count = fs;

		p = bch->fill;

		fillempty = 1;

		fillempty = true;

	} else {

		count = bch->tx_skb->len - bch->tx_idx;

		if (count <= 0)
@@ -477,7 +478,7 @@ hdlc_fill_fifo(struct bchannel *bch) 
			hdlc->ctrl.sr.cmd |= HDLC_CMD_XME;

	}

	ptr = (u32 *)p;

	if (fillempty) {

	if (!fillempty) {

		pr_debug("%s.B%d: %d/%d/%d", fc->name, bch->nr, count,

			 bch->tx_idx, bch->tx_skb->len);

		bch->tx_idx += count;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

+1 −2
Original line number Diff line number Diff line
@@ -9360,8 +9360,7 @@ static int __devinit bnx2x_prev_mark_path(struct bnx2x *bp) 
	struct bnx2x_prev_path_list *tmp_list;

	int rc;



	tmp_list = (struct bnx2x_prev_path_list *)

		    kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);

	tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);

	if (!tmp_list) {

		BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");

		return -ENOMEM;

drivers/net/ethernet/broadcom/tg3.c

+66 −5
Original line number Diff line number Diff line
@@ -92,7 +92,7 @@ static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits) 


#define DRV_MODULE_NAME		"tg3"

#define TG3_MAJ_NUM			3

#define TG3_MIN_NUM			123

#define TG3_MIN_NUM			124

#define DRV_MODULE_VERSION	\

	__stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)

#define DRV_MODULE_RELDATE	"March 21, 2012"
@@ -672,6 +672,12 @@ static int tg3_ape_lock(struct tg3 *tp, int locknum) 
		else

			bit = 1 << tp->pci_fn;

		break;

	case TG3_APE_LOCK_PHY0:

	case TG3_APE_LOCK_PHY1:

	case TG3_APE_LOCK_PHY2:

	case TG3_APE_LOCK_PHY3:

		bit = APE_LOCK_REQ_DRIVER;

		break;

	default:

		return -EINVAL;

	}
@@ -723,6 +729,12 @@ static void tg3_ape_unlock(struct tg3 *tp, int locknum) 
		else

			bit = 1 << tp->pci_fn;

		break;

	case TG3_APE_LOCK_PHY0:

	case TG3_APE_LOCK_PHY1:

	case TG3_APE_LOCK_PHY2:

	case TG3_APE_LOCK_PHY3:

		bit = APE_LOCK_GRANT_DRIVER;

		break;

	default:

		return;

	}
@@ -1052,6 +1064,8 @@ static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) 
		udelay(80);

	}



	tg3_ape_lock(tp, tp->phy_ape_lock);



	*val = 0x0;



	frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
@@ -1086,6 +1100,8 @@ static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) 
		udelay(80);

	}



	tg3_ape_unlock(tp, tp->phy_ape_lock);



	return ret;

}
@@ -1105,6 +1121,8 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val) 
		udelay(80);

	}



	tg3_ape_lock(tp, tp->phy_ape_lock);



	frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &

		      MI_COM_PHY_ADDR_MASK);

	frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
@@ -1135,6 +1153,8 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val) 
		udelay(80);

	}



	tg3_ape_unlock(tp, tp->phy_ape_lock);



	return ret;

}
@@ -9066,8 +9086,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) 
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||

	    tg3_flag(tp, 57765_PLUS)) {

		val = tr32(TG3_RDMA_RSRVCTRL_REG);

		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||

		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {

		if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0) {

			val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |

				 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |

				 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
@@ -9257,6 +9276,19 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) 
	tw32_f(RDMAC_MODE, rdmac_mode);

	udelay(40);



	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {

		for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {

			if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))

				break;

		}

		if (i < TG3_NUM_RDMA_CHANNELS) {

			val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);

			val |= TG3_LSO_RD_DMA_TX_LENGTH_WA;

			tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);

			tg3_flag_set(tp, 5719_RDMA_BUG);

		}

	}



	tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);

	if (!tg3_flag(tp, 5705_PLUS))

		tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
@@ -9616,6 +9648,16 @@ static void tg3_periodic_fetch_stats(struct tg3 *tp) 
	TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);

	TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);

	TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);

	if (unlikely(tg3_flag(tp, 5719_RDMA_BUG) &&

		     (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +

		      sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {

		u32 val;



		val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);

		val &= ~TG3_LSO_RD_DMA_TX_LENGTH_WA;

		tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);

		tg3_flag_clear(tp, 5719_RDMA_BUG);

	}



	TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);

	TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
@@ -12482,10 +12524,12 @@ static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev, 
{

	struct tg3 *tp = netdev_priv(dev);



	if (!tp->hw_stats)

	spin_lock_bh(&tp->lock);

	if (!tp->hw_stats) {

		spin_unlock_bh(&tp->lock);

		return &tp->net_stats_prev;

	}



	spin_lock_bh(&tp->lock);

	tg3_get_nstats(tp, stats);

	spin_unlock_bh(&tp->lock);
@@ -13648,6 +13692,23 @@ static int __devinit tg3_phy_probe(struct tg3 *tp) 
	tg3_flag_set(tp, PAUSE_AUTONEG);

	tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;



	if (tg3_flag(tp, ENABLE_APE)) {

		switch (tp->pci_fn) {

		case 0:

			tp->phy_ape_lock = TG3_APE_LOCK_PHY0;

			break;

		case 1:

			tp->phy_ape_lock = TG3_APE_LOCK_PHY1;

			break;

		case 2:

			tp->phy_ape_lock = TG3_APE_LOCK_PHY2;

			break;

		case 3:

			tp->phy_ape_lock = TG3_APE_LOCK_PHY3;

			break;

		}

	}



	if (tg3_flag(tp, USE_PHYLIB))

		return tg3_phy_init(tp);

drivers/net/ethernet/broadcom/tg3.h

+7 −1
Original line number Diff line number Diff line
@@ -1376,7 +1376,11 @@ 
#define TG3_LSO_RD_DMA_CRPTEN_CTRL	0x00004910

#define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K	 0x00030000

#define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K	 0x000c0000

/* 0x4914 --> 0x4c00 unused */

#define TG3_LSO_RD_DMA_TX_LENGTH_WA	 0x02000000

/* 0x4914 --> 0x4be0 unused */



#define TG3_NUM_RDMA_CHANNELS		4

#define TG3_RDMA_LENGTH			0x00004be0



/* Write DMA control registers */

#define WDMAC_MODE			0x00004c00
@@ -2959,6 +2963,7 @@ enum TG3_FLAGS { 
	TG3_FLAG_L1PLLPD_EN,

	TG3_FLAG_APE_HAS_NCSI,

	TG3_FLAG_4K_FIFO_LIMIT,

	TG3_FLAG_5719_RDMA_BUG,

	TG3_FLAG_RESET_TASK_PENDING,

	TG3_FLAG_5705_PLUS,

	TG3_FLAG_IS_5788,
@@ -3107,6 +3112,7 @@ struct tg3 { 
	int				old_link;



	u8				phy_addr;

	u8				phy_ape_lock;



	/* PHY info */

	u32				phy_id;