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Commit fd04f068 authored by David Dai's avatar David Dai
Browse files

clk: dt-bindings: add clock IDs for Lahaina clock controllers 



Add clock ID constants for all Qualcomm Technologies, Inc. Lahaina
clock controllers which consumers can use to reference individual
clocks.

Change-Id: Id60f27989a773b02ff08278eb430a3314132198c
Signed-off-by: default avatarDavid Dai <daidavid1@codeaurora.org>
parent 9b450de0

include/dt-bindings/clock/qcom,aop-qmp.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/* Copyright (c) 2019, The Linux Foundation. All rights reserved. */



#ifndef _DT_BINDINGS_CLK_QCOM_AOP_QMP_H

#define _DT_BINDINGS_CLK_QCOM_AOP_QMP_H



#define QDSS_CLK_LEVEL_OFF		0

#define QDSS_CLK_LEVEL_DYNAMIC		1

#define QDSS_CLK_LEVEL_TURBO		2

#define QDSS_CLK_LEVEL_NOMINAL		3

#define QDSS_CLK_LEVEL_SVS_L1		4

#define QDSS_CLK_LEVEL_SVS		5

#define QDSS_CLK_LEVEL_LOW_SVS		6

#define QDSS_CLK_LEVEL_MIN_SVS		7



/* clocks id */

#define QDSS_CLK			0

#define QDSS_AO_CLK			1

#endif

include/dt-bindings/clock/qcom,camcc-lahaina.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_LAHAINA_H

#define _DT_BINDINGS_CLK_QCOM_CAM_CC_LAHAINA_H



/* CAM_CC clocks */

#define CAM_CC_BPS_AHB_CLK					0

#define CAM_CC_BPS_AREG_CLK					1

#define CAM_CC_BPS_AXI_CLK					2

#define CAM_CC_BPS_CLK						3

#define CAM_CC_BPS_CLK_SRC					4

#define CAM_CC_CAMNOC_AXI_CLK					5

#define CAM_CC_CAMNOC_AXI_CLK_SRC				6

#define CAM_CC_CAMNOC_DCD_XO_CLK				7

#define CAM_CC_CCI_0_CLK					8

#define CAM_CC_CCI_0_CLK_SRC					9

#define CAM_CC_CCI_1_CLK					10

#define CAM_CC_CCI_1_CLK_SRC					11

#define CAM_CC_CORE_AHB_CLK					12

#define CAM_CC_CPAS_AHB_CLK					13

#define CAM_CC_CPHY_RX_CLK_SRC					14

#define CAM_CC_CSI0PHYTIMER_CLK					15

#define CAM_CC_CSI0PHYTIMER_CLK_SRC				16

#define CAM_CC_CSI1PHYTIMER_CLK					17

#define CAM_CC_CSI1PHYTIMER_CLK_SRC				18

#define CAM_CC_CSI2PHYTIMER_CLK					19

#define CAM_CC_CSI2PHYTIMER_CLK_SRC				20

#define CAM_CC_CSI3PHYTIMER_CLK					21

#define CAM_CC_CSI3PHYTIMER_CLK_SRC				22

#define CAM_CC_CSI4PHYTIMER_CLK					23

#define CAM_CC_CSI4PHYTIMER_CLK_SRC				24

#define CAM_CC_CSI5PHYTIMER_CLK					25

#define CAM_CC_CSI5PHYTIMER_CLK_SRC				26

#define CAM_CC_CSIPHY0_CLK					27

#define CAM_CC_CSIPHY1_CLK					28

#define CAM_CC_CSIPHY2_CLK					29

#define CAM_CC_CSIPHY3_CLK					30

#define CAM_CC_CSIPHY4_CLK					31

#define CAM_CC_CSIPHY5_CLK					32

#define CAM_CC_FAST_AHB_CLK_SRC					33

#define CAM_CC_GDSC_CLK						34

#define CAM_CC_ICP_AHB_CLK					35

#define CAM_CC_ICP_CLK						36

#define CAM_CC_ICP_CLK_SRC					37

#define CAM_CC_IFE_0_AHB_CLK					38

#define CAM_CC_IFE_0_AREG_CLK					39

#define CAM_CC_IFE_0_AXI_CLK					40

#define CAM_CC_IFE_0_CLK					41

#define CAM_CC_IFE_0_CLK_SRC					42

#define CAM_CC_IFE_0_CPHY_RX_CLK				43

#define CAM_CC_IFE_0_CSID_CLK					44

#define CAM_CC_IFE_0_CSID_CLK_SRC				45

#define CAM_CC_IFE_0_DSP_CLK					46

#define CAM_CC_IFE_1_AHB_CLK					47

#define CAM_CC_IFE_1_AREG_CLK					48

#define CAM_CC_IFE_1_AXI_CLK					49

#define CAM_CC_IFE_1_CLK					50

#define CAM_CC_IFE_1_CLK_SRC					51

#define CAM_CC_IFE_1_CPHY_RX_CLK				52

#define CAM_CC_IFE_1_CSID_CLK					53

#define CAM_CC_IFE_1_CSID_CLK_SRC				54

#define CAM_CC_IFE_1_DSP_CLK					55

#define CAM_CC_IFE_2_AHB_CLK					56

#define CAM_CC_IFE_2_AREG_CLK					57

#define CAM_CC_IFE_2_AXI_CLK					58

#define CAM_CC_IFE_2_CLK					59

#define CAM_CC_IFE_2_CLK_SRC					60

#define CAM_CC_IFE_2_CPHY_RX_CLK				61

#define CAM_CC_IFE_2_CSID_CLK					62

#define CAM_CC_IFE_2_CSID_CLK_SRC				63

#define CAM_CC_IFE_LITE_AHB_CLK					64

#define CAM_CC_IFE_LITE_AXI_CLK					65

#define CAM_CC_IFE_LITE_CLK					66

#define CAM_CC_IFE_LITE_CLK_SRC					67

#define CAM_CC_IFE_LITE_CPHY_RX_CLK				68

#define CAM_CC_IFE_LITE_CSID_CLK				69

#define CAM_CC_IFE_LITE_CSID_CLK_SRC				70

#define CAM_CC_IPE_0_AHB_CLK					71

#define CAM_CC_IPE_0_AREG_CLK					72

#define CAM_CC_IPE_0_AXI_CLK					73

#define CAM_CC_IPE_0_CLK					74

#define CAM_CC_IPE_0_CLK_SRC					75

#define CAM_CC_JPEG_CLK						76

#define CAM_CC_JPEG_CLK_SRC					77

#define CAM_CC_MCLK0_CLK					78

#define CAM_CC_MCLK0_CLK_SRC					79

#define CAM_CC_MCLK1_CLK					80

#define CAM_CC_MCLK1_CLK_SRC					81

#define CAM_CC_MCLK2_CLK					82

#define CAM_CC_MCLK2_CLK_SRC					83

#define CAM_CC_MCLK3_CLK					84

#define CAM_CC_MCLK3_CLK_SRC					85

#define CAM_CC_MCLK4_CLK					86

#define CAM_CC_MCLK4_CLK_SRC					87

#define CAM_CC_MCLK5_CLK					88

#define CAM_CC_MCLK5_CLK_SRC					89

#define CAM_CC_PLL0						90

#define CAM_CC_PLL0_OUT_EVEN					91

#define CAM_CC_PLL0_OUT_ODD					92

#define CAM_CC_PLL1						93

#define CAM_CC_PLL1_OUT_EVEN					94

#define CAM_CC_PLL2						95

#define CAM_CC_PLL3						96

#define CAM_CC_PLL3_OUT_EVEN					97

#define CAM_CC_PLL4						98

#define CAM_CC_PLL4_OUT_EVEN					99

#define CAM_CC_PLL5						100

#define CAM_CC_PLL5_OUT_EVEN					101

#define CAM_CC_PLL6						102

#define CAM_CC_PLL6_OUT_EVEN					103

#define CAM_CC_SBI_AHB_CLK					104

#define CAM_CC_SBI_AXI_CLK					105

#define CAM_CC_SBI_CLK						106

#define CAM_CC_SBI_CPHY_RX_0_CLK				107

#define CAM_CC_SBI_CPHY_RX_1_CLK				108

#define CAM_CC_SBI_CSID_0_CLK					109

#define CAM_CC_SBI_CSID_1_CLK					110

#define CAM_CC_SBI_CSID_CLK_SRC					111

#define CAM_CC_SBI_DIV_CLK_SRC					112

#define CAM_CC_SBI_IFE_0_CLK					113

#define CAM_CC_SBI_IFE_1_CLK					114

#define CAM_CC_SBI_IFE_2_CLK					115

#define CAM_CC_SLEEP_CLK					116

#define CAM_CC_SLEEP_CLK_SRC					117

#define CAM_CC_SLOW_AHB_CLK_SRC					118

#define CAM_CC_XO_CLK_SRC					119



/* CAM_CC resets */

#define CAM_CC_BPS_BCR						0

#define CAM_CC_ICP_BCR						1

#define CAM_CC_IFE_0_BCR					2

#define CAM_CC_IFE_1_BCR					3

#define CAM_CC_IFE_2_BCR					4

#define CAM_CC_IPE_0_BCR					5

#define CAM_CC_SBI_BCR						6



#endif

include/dt-bindings/clock/qcom,dispcc-lahaina.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_LAHAINA_H

#define _DT_BINDINGS_CLK_QCOM_DISP_CC_LAHAINA_H



/* DISP_CC clocks */

#define DISP_CC_MDSS_AHB_CLK					0

#define DISP_CC_MDSS_AHB_CLK_SRC				1

#define DISP_CC_MDSS_BYTE0_CLK					2

#define DISP_CC_MDSS_BYTE0_CLK_SRC				3

#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC				4

#define DISP_CC_MDSS_BYTE0_INTF_CLK				5

#define DISP_CC_MDSS_BYTE1_CLK					6

#define DISP_CC_MDSS_BYTE1_CLK_SRC				7

#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC				8

#define DISP_CC_MDSS_BYTE1_INTF_CLK				9

#define DISP_CC_MDSS_DP_AUX1_CLK				10

#define DISP_CC_MDSS_DP_AUX1_CLK_SRC				11

#define DISP_CC_MDSS_DP_AUX_CLK					12

#define DISP_CC_MDSS_DP_AUX_CLK_SRC				13

#define DISP_CC_MDSS_DP_CRYPTO1_CLK				14

#define DISP_CC_MDSS_DP_CRYPTO1_CLK_SRC				15

#define DISP_CC_MDSS_DP_CRYPTO_CLK				16

#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC				17

#define DISP_CC_MDSS_DP_LINK1_CLK				18

#define DISP_CC_MDSS_DP_LINK1_CLK_SRC				19

#define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC			20

#define DISP_CC_MDSS_DP_LINK1_INTF_CLK				21

#define DISP_CC_MDSS_DP_LINK_CLK				22

#define DISP_CC_MDSS_DP_LINK_CLK_SRC				23

#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC			24

#define DISP_CC_MDSS_DP_LINK_INTF_CLK				25

#define DISP_CC_MDSS_DP_PIXEL1_CLK				26

#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC				27

#define DISP_CC_MDSS_DP_PIXEL2_CLK				28

#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC				29

#define DISP_CC_MDSS_DP_PIXEL_CLK				30

#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC				31

#define DISP_CC_MDSS_EDP_AUX_CLK				32

#define DISP_CC_MDSS_EDP_AUX_CLK_SRC				33

#define DISP_CC_MDSS_EDP_LINK_CLK				34

#define DISP_CC_MDSS_EDP_LINK_CLK_SRC				35

#define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC			36

#define DISP_CC_MDSS_EDP_LINK_INTF_CLK				37

#define DISP_CC_MDSS_EDP_PIXEL_CLK				38

#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC				39

#define DISP_CC_MDSS_ESC0_CLK					40

#define DISP_CC_MDSS_ESC0_CLK_SRC				41

#define DISP_CC_MDSS_ESC1_CLK					42

#define DISP_CC_MDSS_ESC1_CLK_SRC				43

#define DISP_CC_MDSS_MDP_CLK					44

#define DISP_CC_MDSS_MDP_CLK_SRC				45

#define DISP_CC_MDSS_MDP_LUT_CLK				46

#define DISP_CC_MDSS_NON_GDSC_AHB_CLK				47

#define DISP_CC_MDSS_PCLK0_CLK					48

#define DISP_CC_MDSS_PCLK0_CLK_SRC				49

#define DISP_CC_MDSS_PCLK1_CLK					50

#define DISP_CC_MDSS_PCLK1_CLK_SRC				51

#define DISP_CC_MDSS_ROT_CLK					52

#define DISP_CC_MDSS_ROT_CLK_SRC				53

#define DISP_CC_MDSS_RSCC_AHB_CLK				54

#define DISP_CC_MDSS_RSCC_VSYNC_CLK				55

#define DISP_CC_MDSS_VSYNC_CLK					56

#define DISP_CC_MDSS_VSYNC_CLK_SRC				57

#define DISP_CC_PLL0						58

#define DISP_CC_PLL1						59

#define DISP_CC_SLEEP_CLK					60

#define DISP_CC_SLEEP_CLK_SRC					61

#define DISP_CC_XO_CLK						62

#define DISP_CC_XO_CLK_SRC					63



/* DISP_CC resets */

#define DISP_CC_MDSS_CORE_BCR					0

#define DISP_CC_MDSS_RSCC_BCR					1



#endif

include/dt-bindings/clock/qcom,gcc-lahaina.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_GCC_LAHAINA_H

#define _DT_BINDINGS_CLK_QCOM_GCC_LAHAINA_H



/* GCC clocks */

#define CORE_BI_PLL_TEST_SE					0

#define GCC_AGGRE_NOC_PCIE_TBU_CLK				1

#define GCC_AGGRE_UFS_CARD_AXI_CLK				2

#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK			3

#define GCC_AGGRE_UFS_PHY_AXI_CLK				4

#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK			5

#define GCC_AGGRE_USB3_PRIM_AXI_CLK				6

#define GCC_AGGRE_USB3_SEC_AXI_CLK				7

#define GCC_BOOT_ROM_AHB_CLK					8

#define GCC_CAMERA_AHB_CLK					9

#define GCC_CAMERA_HF_AXI_CLK					10

#define GCC_CAMERA_SF_AXI_CLK					11

#define GCC_CAMERA_XO_CLK					12

#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				13

#define GCC_CFG_NOC_USB3_SEC_AXI_CLK				14

#define GCC_CPUSS_AHB_CLK					15

#define GCC_CPUSS_AHB_CLK_SRC					16

#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC				17

#define GCC_DDRSS_GPU_AXI_CLK					18

#define GCC_DDRSS_PCIE_SF_TBU_CLK				19

#define GCC_DISP_AHB_CLK					20

#define GCC_DISP_HF_AXI_CLK					21

#define GCC_DISP_SF_AXI_CLK					22

#define GCC_DISP_XO_CLK						23

#define GCC_DPM_CB_CLK						24

#define GCC_DPM_CLK						25

#define GCC_DPM_CLK_SRC						26

#define GCC_DPM_CX_AHB_CLK					27

#define GCC_DPM_MX_AHB_CLK					28

#define GCC_GP1_CLK						29

#define GCC_GP1_CLK_SRC						30

#define GCC_GP2_CLK						31

#define GCC_GP2_CLK_SRC						32

#define GCC_GP3_CLK						33

#define GCC_GP3_CLK_SRC						34

#define GCC_GPLL0						35

#define GCC_GPLL0_OUT_EVEN					36

#define GCC_GPLL9						37

#define GCC_GPU_CFG_AHB_CLK					38

#define GCC_GPU_GPLL0_CLK_SRC					39

#define GCC_GPU_GPLL0_DIV_CLK_SRC				40

#define GCC_GPU_IREF_EN						41

#define GCC_GPU_MEMNOC_GFX_CLK					42

#define GCC_GPU_SNOC_DVM_GFX_CLK				43

#define GCC_PCIE0_PHY_RCHNG_CLK					44

#define GCC_PCIE1_PHY_RCHNG_CLK					45

#define GCC_PCIE_0_AUX_CLK					46

#define GCC_PCIE_0_AUX_CLK_SRC					47

#define GCC_PCIE_0_CFG_AHB_CLK					48

#define GCC_PCIE_0_CLKREF_EN					49

#define GCC_PCIE_0_MSTR_AXI_CLK					50

#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC				51

#define GCC_PCIE_0_PIPE_CLK					52

#define GCC_PCIE_0_SLV_AXI_CLK					53

#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				54

#define GCC_PCIE_1_AUX_CLK					55

#define GCC_PCIE_1_AUX_CLK_SRC					56

#define GCC_PCIE_1_CFG_AHB_CLK					57

#define GCC_PCIE_1_CLKREF_EN					58

#define GCC_PCIE_1_MSTR_AXI_CLK					59

#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC				60

#define GCC_PCIE_1_PIPE_CLK					61

#define GCC_PCIE_1_SLV_AXI_CLK					62

#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				63

#define GCC_PDM2_CLK						64

#define GCC_PDM2_CLK_SRC					65

#define GCC_PDM_AHB_CLK						66

#define GCC_PDM_XO4_CLK						67

#define GCC_QMIP_CAMERA_NRT_AHB_CLK				68

#define GCC_QMIP_CAMERA_RT_AHB_CLK				69

#define GCC_QMIP_DISP_AHB_CLK					70

#define GCC_QMIP_VIDEO_CVP_AHB_CLK				71

#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				72

#define GCC_QUPV3_WRAP0_CORE_2X_CLK				73

#define GCC_QUPV3_WRAP0_CORE_CLK				74

#define GCC_QUPV3_WRAP0_S0_CLK					75

#define GCC_QUPV3_WRAP0_S0_CLK_SRC				76

#define GCC_QUPV3_WRAP0_S1_CLK					77

#define GCC_QUPV3_WRAP0_S1_CLK_SRC				78

#define GCC_QUPV3_WRAP0_S2_CLK					79

#define GCC_QUPV3_WRAP0_S2_CLK_SRC				80

#define GCC_QUPV3_WRAP0_S3_CLK					81

#define GCC_QUPV3_WRAP0_S3_CLK_SRC				82

#define GCC_QUPV3_WRAP0_S4_CLK					83

#define GCC_QUPV3_WRAP0_S4_CLK_SRC				84

#define GCC_QUPV3_WRAP0_S5_CLK					85

#define GCC_QUPV3_WRAP0_S5_CLK_SRC				86

#define GCC_QUPV3_WRAP0_S6_CLK					87

#define GCC_QUPV3_WRAP0_S6_CLK_SRC				88

#define GCC_QUPV3_WRAP0_S7_CLK					89

#define GCC_QUPV3_WRAP0_S7_CLK_SRC				90

#define GCC_QUPV3_WRAP1_CORE_2X_CLK				91

#define GCC_QUPV3_WRAP1_CORE_CLK				92

#define GCC_QUPV3_WRAP1_S0_CLK					93

#define GCC_QUPV3_WRAP1_S0_CLK_SRC				94

#define GCC_QUPV3_WRAP1_S1_CLK					95

#define GCC_QUPV3_WRAP1_S1_CLK_SRC				96

#define GCC_QUPV3_WRAP1_S2_CLK					97

#define GCC_QUPV3_WRAP1_S2_CLK_SRC				98

#define GCC_QUPV3_WRAP1_S3_CLK					99

#define GCC_QUPV3_WRAP1_S3_CLK_SRC				100

#define GCC_QUPV3_WRAP1_S4_CLK					101

#define GCC_QUPV3_WRAP1_S4_CLK_SRC				102

#define GCC_QUPV3_WRAP1_S5_CLK					103

#define GCC_QUPV3_WRAP1_S5_CLK_SRC				104

#define GCC_QUPV3_WRAP2_CORE_2X_CLK				105

#define GCC_QUPV3_WRAP2_CORE_CLK				106

#define GCC_QUPV3_WRAP2_S0_CLK					107

#define GCC_QUPV3_WRAP2_S0_CLK_SRC				108

#define GCC_QUPV3_WRAP2_S1_CLK					109

#define GCC_QUPV3_WRAP2_S1_CLK_SRC				110

#define GCC_QUPV3_WRAP2_S2_CLK					111

#define GCC_QUPV3_WRAP2_S2_CLK_SRC				112

#define GCC_QUPV3_WRAP2_S3_CLK					113

#define GCC_QUPV3_WRAP2_S3_CLK_SRC				114

#define GCC_QUPV3_WRAP2_S4_CLK					115

#define GCC_QUPV3_WRAP2_S4_CLK_SRC				116

#define GCC_QUPV3_WRAP2_S5_CLK					117

#define GCC_QUPV3_WRAP2_S5_CLK_SRC				118

#define GCC_QUPV3_WRAP_0_M_AHB_CLK				119

#define GCC_QUPV3_WRAP_0_S_AHB_CLK				120

#define GCC_QUPV3_WRAP_1_M_AHB_CLK				121

#define GCC_QUPV3_WRAP_1_S_AHB_CLK				122

#define GCC_QUPV3_WRAP_2_M_AHB_CLK				123

#define GCC_QUPV3_WRAP_2_S_AHB_CLK				124

#define GCC_SDCC2_AHB_CLK					125

#define GCC_SDCC2_APPS_CLK					126

#define GCC_SDCC2_APPS_CLK_SRC					127

#define GCC_SDCC4_AHB_CLK					128

#define GCC_SDCC4_APPS_CLK					129

#define GCC_SDCC4_APPS_CLK_SRC					130

#define GCC_SYS_NOC_CPUSS_AHB_CLK				131

#define GCC_UFS_1_CLKREF_EN					132

#define GCC_UFS_CARD_AHB_CLK					133

#define GCC_UFS_CARD_AXI_CLK					134

#define GCC_UFS_CARD_AXI_CLK_SRC				135

#define GCC_UFS_CARD_AXI_HW_CTL_CLK				136

#define GCC_UFS_CARD_ICE_CORE_CLK				137

#define GCC_UFS_CARD_ICE_CORE_CLK_SRC				138

#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK			139

#define GCC_UFS_CARD_PHY_AUX_CLK				140

#define GCC_UFS_CARD_PHY_AUX_CLK_SRC				141

#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK				142

#define GCC_UFS_CARD_RX_SYMBOL_0_CLK				143

#define GCC_UFS_CARD_RX_SYMBOL_1_CLK				144

#define GCC_UFS_CARD_TX_SYMBOL_0_CLK				145

#define GCC_UFS_CARD_UNIPRO_CORE_CLK				146

#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC			147

#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK			148

#define GCC_UFS_PHY_AHB_CLK					149

#define GCC_UFS_PHY_AXI_CLK					150

#define GCC_UFS_PHY_AXI_CLK_SRC					151

#define GCC_UFS_PHY_AXI_HW_CTL_CLK				152

#define GCC_UFS_PHY_ICE_CORE_CLK				153

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				154

#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK				155

#define GCC_UFS_PHY_PHY_AUX_CLK					156

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				157

#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK				158

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				159

#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				160

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				161

#define GCC_UFS_PHY_UNIPRO_CORE_CLK				162

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				163

#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK			164

#define GCC_USB30_PRIM_MASTER_CLK				165

#define GCC_USB30_PRIM_MASTER_CLK_SRC				166

#define GCC_USB30_PRIM_MOCK_UTMI_CLK				167

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			168

#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC		169

#define GCC_USB30_PRIM_SLEEP_CLK				170

#define GCC_USB30_SEC_MASTER_CLK				171

#define GCC_USB30_SEC_MASTER_CLK_SRC				172

#define GCC_USB30_SEC_MOCK_UTMI_CLK				173

#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				174

#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC			175

#define GCC_USB30_SEC_SLEEP_CLK					176

#define GCC_USB3_PRIM_PHY_AUX_CLK				177

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				178

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				179

#define GCC_USB3_PRIM_PHY_PIPE_CLK				180

#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC				181

#define GCC_USB3_SEC_CLKREF_EN					182

#define GCC_USB3_SEC_PHY_AUX_CLK				183

#define GCC_USB3_SEC_PHY_AUX_CLK_SRC				184

#define GCC_USB3_SEC_PHY_COM_AUX_CLK				185

#define GCC_USB3_SEC_PHY_PIPE_CLK				186

#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC				187

#define GCC_VIDEO_AHB_CLK					188

#define GCC_VIDEO_AXI0_CLK					189

#define GCC_VIDEO_AXI1_CLK					190

#define GCC_VIDEO_XO_CLK					191

#define USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK			192

#define USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK			193



/* GCC resets */

#define GCC_CAMERA_BCR						0

#define GCC_DISPLAY_BCR						1

#define GCC_DPM_BCR						2

#define GCC_GPU_BCR						3

#define GCC_MMSS_BCR						4

#define GCC_PCIE_0_BCR						5

#define GCC_PCIE_0_LINK_DOWN_BCR				6

#define GCC_PCIE_0_NOCSR_COM_PHY_BCR				7

#define GCC_PCIE_0_PHY_BCR					8

#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR			9

#define GCC_PCIE_1_BCR						10

#define GCC_PCIE_1_LINK_DOWN_BCR				11

#define GCC_PCIE_1_NOCSR_COM_PHY_BCR				12

#define GCC_PCIE_1_PHY_BCR					13

#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR			14

#define GCC_PCIE_PHY_CFG_AHB_BCR				15

#define GCC_PCIE_PHY_COM_BCR					16

#define GCC_PDM_BCR						17

#define GCC_QUPV3_WRAPPER_0_BCR					18

#define GCC_QUPV3_WRAPPER_1_BCR					19

#define GCC_QUPV3_WRAPPER_2_BCR					20

#define GCC_QUSB2PHY_PRIM_BCR					21

#define GCC_QUSB2PHY_SEC_BCR					22

#define GCC_SDCC2_BCR						23

#define GCC_SDCC4_BCR						24

#define GCC_UFS_CARD_BCR					25

#define GCC_UFS_PHY_BCR						26

#define GCC_USB30_PRIM_BCR					27

#define GCC_USB30_SEC_BCR					28

#define GCC_USB3_DP_PHY_PRIM_BCR				29

#define GCC_USB3_DP_PHY_SEC_BCR					30

#define GCC_USB3_PHY_PRIM_BCR					31

#define GCC_USB3_PHY_SEC_BCR					32

#define GCC_USB3PHY_PHY_PRIM_BCR				33

#define GCC_USB3PHY_PHY_SEC_BCR					34

#define GCC_USB_PHY_CFG_AHB2PHY_BCR				35

#define GCC_VIDEO_AXI0_CLK_ARES					36

#define GCC_VIDEO_AXI1_CLK_ARES					37

#define GCC_VIDEO_BCR						38



#endif

include/dt-bindings/clock/qcom,gpucc-lahaina.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_LAHAINA_H

#define _DT_BINDINGS_CLK_QCOM_GPU_CC_LAHAINA_H



/* GPU_CC clocks */

#define GPU_CC_AHB_CLK						0

#define GPU_CC_CB_CLK						1

#define GPU_CC_CRC_AHB_CLK					2

#define GPU_CC_CX_APB_CLK					3

#define GPU_CC_CX_GMU_CLK					4

#define GPU_CC_CX_QDSS_AT_CLK					5

#define GPU_CC_CX_QDSS_TRIG_CLK					6

#define GPU_CC_CX_QDSS_TSCTR_CLK				7

#define GPU_CC_CX_SNOC_DVM_CLK					8

#define GPU_CC_CXO_AON_CLK					9

#define GPU_CC_CXO_CLK						10

#define GPU_CC_FREQ_MEASURE_CLK					11

#define GPU_CC_GMU_CLK_SRC					12

#define GPU_CC_GX_GMU_CLK					13

#define GPU_CC_GX_QDSS_TSCTR_CLK				14

#define GPU_CC_GX_VSENSE_CLK					15

#define GPU_CC_HUB_AHB_DIV_CLK_SRC				16

#define GPU_CC_HUB_AON_CLK					17

#define GPU_CC_HUB_CLK_SRC					18

#define GPU_CC_HUB_CX_INT_CLK					19

#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC				20

#define GPU_CC_MND1X_0_GFX3D_CLK				21

#define GPU_CC_MND1X_1_GFX3D_CLK				22

#define GPU_CC_PLL1						23

#define GPU_CC_SLEEP_CLK					24



/* GPU_CC resets */

#define GPUCC_GPU_CC_ACD_BCR					0

#define GPUCC_GPU_CC_CB_BCR					1

#define GPUCC_GPU_CC_CX_BCR					2

#define GPUCC_GPU_CC_FAST_HUB_BCR				3

#define GPUCC_GPU_CC_GFX3D_AON_BCR				4

#define GPUCC_GPU_CC_GMU_BCR					5

#define GPUCC_GPU_CC_GX_BCR					6

#define GPUCC_GPU_CC_XO_BCR					7



#endif