Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit fce695cb authored by Ryder Lee's avatar Ryder Lee Committed by Matthias Brugger
Browse files

arm: dts: mt7623: add iommu/smi device nodes 



Add iommu/smi device nodes for MT7623.

Signed-off-by: default avatarRyder Lee <ryder.lee@mediatek.com>
Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 8ff2017b

arch/arm/boot/dts/mt7623.dtsi

+59 −0
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#include <dt-bindings/power/mt2701-power.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/phy/phy.h>

#include <dt-bindings/memory/mt2701-larb-port.h>

#include <dt-bindings/reset/mt2701-resets.h>

#include <dt-bindings/thermal/thermal.h>
@@ -286,6 +287,17 @@ 
		clock-names = "system-clk", "rtc-clk";

	};



	smi_common: smi@1000c000 {

		compatible = "mediatek,mt7623-smi-common",

			     "mediatek,mt2701-smi-common";

		reg = <0 0x1000c000 0 0x1000>;

		clocks = <&infracfg CLK_INFRA_SMI>,

			 <&mmsys CLK_MM_SMI_COMMON>,

			 <&infracfg CLK_INFRA_SMI>;

		clock-names = "apb", "smi", "async";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;

	};



	pwrap: pwrap@1000d000 {

		compatible = "mediatek,mt7623-pwrap",

			     "mediatek,mt2701-pwrap";
@@ -317,6 +329,17 @@ 
		reg = <0 0x10200100 0 0x1c>;

	};



	iommu: mmsys_iommu@10205000 {

		compatible = "mediatek,mt7623-m4u",

			     "mediatek,mt2701-m4u";

		reg = <0 0x10205000 0 0x1000>;

		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&infracfg CLK_INFRA_M4U>;

		clock-names = "bclk";

		mediatek,larbs = <&larb0 &larb1 &larb2>;

		#iommu-cells = <1>;

	};



	efuse: efuse@10206000 {

		compatible = "mediatek,mt7623-efuse",

			     "mediatek,mt8173-efuse";
@@ -709,6 +732,18 @@ 
		#clock-cells = <1>;

	};



	larb0: larb@14010000 {

		compatible = "mediatek,mt7623-smi-larb",

			     "mediatek,mt2701-smi-larb";

		reg = <0 0x14010000 0 0x1000>;

		mediatek,smi = <&smi_common>;

		mediatek,larb-id = <0>;

		clocks = <&mmsys CLK_MM_SMI_LARB0>,

			 <&mmsys CLK_MM_SMI_LARB0>;

		clock-names = "apb", "smi";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;

	};



	imgsys: syscon@15000000 {

		compatible = "mediatek,mt7623-imgsys",

			     "mediatek,mt2701-imgsys",
@@ -717,6 +752,18 @@ 
		#clock-cells = <1>;

	};



	larb2: larb@15001000 {

		compatible = "mediatek,mt7623-smi-larb",

			     "mediatek,mt2701-smi-larb";

		reg = <0 0x15001000 0 0x1000>;

		mediatek,smi = <&smi_common>;

		mediatek,larb-id = <2>;

		clocks = <&imgsys CLK_IMG_SMI_COMM>,

			 <&imgsys CLK_IMG_SMI_COMM>;

		clock-names = "apb", "smi";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;

	};



	vdecsys: syscon@16000000 {

		compatible = "mediatek,mt7623-vdecsys",

			     "mediatek,mt2701-vdecsys",
@@ -725,6 +772,18 @@ 
		#clock-cells = <1>;

	};



	larb1: larb@16010000 {

		compatible = "mediatek,mt7623-smi-larb",

			     "mediatek,mt2701-smi-larb";

		reg = <0 0x16010000 0 0x1000>;

		mediatek,smi = <&smi_common>;

		mediatek,larb-id = <1>;

		clocks = <&vdecsys CLK_VDEC_CKGEN>,

			 <&vdecsys CLK_VDEC_LARB>;

		clock-names = "apb", "smi";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;

	};



	hifsys: syscon@1a000000 {

		compatible = "mediatek,mt7623-hifsys",

			     "mediatek,mt2701-hifsys",