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Commit fcb20cd7 authored by Mayank Grover's avatar Mayank Grover Committed by Ashish Bhimanpalliwar
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ARM: dts: msm: Add initial device tree for Blair

Adding initial device tree support for Blair target.

Change-Id: I9ffe2a86e2a6710968600653fdc7427dacf9b158
parent a08b200c
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+4 −0
Original line number Diff line number Diff line
@@ -101,6 +101,9 @@ SoCs:
- HOLI
  compatible = "qcom,holi"

- BLAIR
  compatible = "qcom,blair"

- MONACO
  compatible = "qcom,monaco"

@@ -284,6 +287,7 @@ compatible = "qcom,holi-mtp"
compatible = "qcom,holi-cdp"
compatible = "qcom,holi-qrd"
compatible = "qcom,holi-atp"
compatible = "qcom,blair-rumi"
compatible = "qcom,scuba-idp"
compatible = "qcom,monaco-rumi"
compatible = "qcom,sdxnightjar-mtp"
+8 −0
Original line number Diff line number Diff line
@@ -125,6 +125,14 @@ dtb-$(CONFIG_ARCH_HOLI) += holi-rumi.dtb \
	holi-mtp-usbc.dtb
endif

ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
dtbo-$(CONFIG_ARCH_BLAIR) += blair-rumi-overlay.dtbo

blair-rumi-overlay.dtbo-base := blair.dtb
else
dtb-$(CONFIG_ARCH_BLAIR) += blair-rumi.dtb
endif

ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
dtbo-$(CONFIG_ARCH_SHIMA) +=    \
	shima-rumi-overlay.dtbo \
+11 −0
Original line number Diff line number Diff line
/dts-v1/;
/plugin/;

#include "blair-rumi.dtsi"

/ {
	model = "Qualcomm Technologies, Inc. Blair RUMI";
	compatible = "qcom,blair-rumi", "qcom,blair", "qcom,rumi";
	qcom,msm-id = <507 0x10000>;
	qcom,board-id = <15 0>;
};

qcom/blair-rumi.dts

0 → 100644
+11 −0
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/dts-v1/;
/memreserve/ 0x50000000 0x00000100;

#include "blair.dtsi"
#include "blair-rumi.dtsi"

/ {
	model = "Qualcomm Technologies, Inc. Blair RUMI";
	compatible = "qcom,blair-rumi", "qcom,blair", "qcom,rumi";
	qcom,board-id = <15 0>;
};

qcom/blair-rumi.dtsi

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+122 −0
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#include <dt-bindings/gpio/gpio.h>
&soc {
	timer {
		clock-frequency = <500000>;
	};

	timer@f420000 {
		clock-frequency = <500000>;
	};

	wdog {
		status = "disabled";
	};

	usb_emu_phy_0: usb_emu_phy@0x04f20000 {
		compatible = "qcom,usb-emu-phy";
		reg = <0x04f20000 0x9500>;

		qcom,emu-init-seq = <0xffff 0x4
				     0xfff0 0x4
				     0x100000 0x20
				     0x0 0x20
				     0x101f0 0x20
				     0x100000 0x3c
				     0x0 0x3c
				     0x10060 0x3c
				     0x0 0x4>;
	};
};

&tsens0 {
	status = "disabled";
};

&tsens1 {
	status = "disabled";
};

&sdhc_1 {
	status = "disabled";

	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&sdc1_on>;
	pinctrl-1 = <&sdc1_off>;

	cap-mmc-highspeed;

	vdd-supply = <&L7E>;
	qcom,vdd-voltage-level = <2960000 2960000>;
	qcom,vdd-current-level = <0 570000>;

	vdd-io-supply = <&L12A>;
	qcom,vdd-io-always-on;
	qcom,vdd-io-lpm-sup;
	qcom,vdd-io-voltage-level = <1800000 1800000>;
	qcom,vdd-io-current-level = <0 325000>;
};

&sdhc_2 {
	status = "ok";

	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&sdc2_on>;
	pinctrl-1 = <&sdc2_off>;

	cap-sd-highspeed;

	vdd-supply = <&L9E>;
	qcom,vdd-voltage-level = <2960000 2960000>;
	qcom,vdd-current-level = <0 800000>;

	vdd-io-supply = <&L6E>;
	qcom,vdd-io-voltage-level = <2960000 2960000>;
	qcom,vdd-io-current-level = <0 22000>;

	cd-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
};

&ufsphy_mem {
		compatible = "qcom,ufs-phy-qrbtc-sdm845";

		vdda-phy-supply = <&L18A>;
		vdda-pll-supply = <&L22A>;
		vdda-phy-max-microamp = <62900>;
		vdda-pll-max-microamp = <18300>;

		status = "ok";
};

&ufshc_mem {

		limit-tx-hs-gear = <1>;
		limit-rx-hs-gear = <1>;
		limit-rate = <1>; /* HS Rate-B */

		vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
		vdd-hba-fixed-regulator;

		vcc-supply = <&L7E>;
		vcc-max-microamp = <800000>;

		vccq2-supply = <&L12A>;
		vccq2-max-microamp = <800000>;

		qcom,vddp-ref-clk-supply = <&L22A>;
		qcom,vddp-ref-clk-max-microamp = <100>;

		qcom,disable-lpm;
		rpm-level = <0>;
		spm-level = <0>;

		status = "ok";
};

/* Debug UART Console */
&qupv3_se9_2uart {
	qcom,rumi_platform;
};

&qupv3_se10_i2c {
	 status = "disabled";
};
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