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Commit fc9cf222 authored by Qiuxu Zhuo's avatar Qiuxu Zhuo Committed by Greg Kroah-Hartman
Browse files

EDAC/i10nm: Fix NVDIMM detection 



[ Upstream commit 2294a7299f5e51667b841f63c6d69474491753fb ]

MCDDRCFG is a per-channel register and uses bit{0,1} to indicate
the NVDIMM presence on DIMM slot{0,1}. Current i10nm_edac driver
wrongly uses MCDDRCFG as per-DIMM register and fails to detect
the NVDIMM.

Fix it by reading MCDDRCFG as per-channel register and using its
bit{0,1} to check whether the NVDIMM is populated on DIMM slot{0,1}.

Fixes: d4dc89d0 ("EDAC, i10nm: Add a driver for Intel 10nm server processors")
Reported-by: default avatarFan Du <fan.du@intel.com>
Tested-by: default avatarWen Jin <wen.jin@intel.com>
Signed-off-by: default avatarQiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
Link: https://lore.kernel.org/r/20210818175701.1611513-2-tony.luck@intel.com


Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 32d8a368

drivers/edac/i10nm_base.c

+3 −3
Original line number Diff line number Diff line
@@ -26,8 +26,8 @@ 
	pci_read_config_dword((d)->uracu, 0xd8 + (i) * 4, &(reg))

#define I10NM_GET_DIMMMTR(m, i, j)	\

	readl((m)->mbase + 0x2080c + (i) * 0x4000 + (j) * 4)

#define I10NM_GET_MCDDRTCFG(m, i, j)	\

	readl((m)->mbase + 0x20970 + (i) * 0x4000 + (j) * 4)

#define I10NM_GET_MCDDRTCFG(m, i)	\

	readl((m)->mbase + 0x20970 + (i) * 0x4000)

#define I10NM_GET_MCMTR(m, i)		\

	readl((m)->mbase + 0x20ef8 + (i) * 0x4000)
@@ -156,11 +156,11 @@ static int i10nm_get_dimm_config(struct mem_ctl_info *mci) 
			continue;



		ndimms = 0;

		mcddrtcfg = I10NM_GET_MCDDRTCFG(imc, i);

		for (j = 0; j < I10NM_NUM_DIMMS; j++) {

			dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,

					     mci->n_layers, i, j, 0);

			mtr = I10NM_GET_DIMMMTR(imc, i, j);

			mcddrtcfg = I10NM_GET_MCDDRTCFG(imc, i, j);

			edac_dbg(1, "dimmmtr 0x%x mcddrtcfg 0x%x (mc%d ch%d dimm%d)\n",

				 mtr, mcddrtcfg, imc->mc, i, j);