Loading qcom/shima.dtsi +1 −21 Original line number Diff line number Diff line Loading @@ -2596,7 +2596,7 @@ cpu4_llcc_ddr_latmon: qcom,cpu4-llcc-ddr-latmon { compatible = "qcom,arm-memlat-mon"; qcom,cpulist = <&CPU4 &CPU5 &CPU6>; qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; qcom,target-dev = <&cpu4_llcc_ddr_lat>; qcom,cachemiss-ev = <0x1000>; ddr4-map { Loading @@ -2623,26 +2623,6 @@ }; }; cpu7_llcc_ddr_latmon: qcom,cpu7-llcc-ddr-latmon { compatible = "qcom,arm-memlat-mon"; qcom,cpulist = <&CPU7>; qcom,target-dev = <&cpu4_llcc_ddr_lat>; qcom,cachemiss-ev = <0x1000>; ddr4-map { qcom,ddr-type = <DDR_TYPE_LPDDR4X>; qcom,core-dev-table = < 2361600 MHZ_TO_MBPS( 300, 4) >, < 2707200 MHZ_TO_MBPS(2133, 4) >; }; ddr5-map { qcom,ddr-type = <DDR_TYPE_LPDDR5>; qcom,core-dev-table = < 2361600 MHZ_TO_MBPS( 300, 4) >, < 2707200 MHZ_TO_MBPS(3196, 4) >; }; }; cpu4_computemon: qcom,cpu4-computemon { compatible = "qcom,arm-compute-mon"; qcom,target-dev = <&cpu4_cpu_ddr_latfloor>; Loading Loading
qcom/shima.dtsi +1 −21 Original line number Diff line number Diff line Loading @@ -2596,7 +2596,7 @@ cpu4_llcc_ddr_latmon: qcom,cpu4-llcc-ddr-latmon { compatible = "qcom,arm-memlat-mon"; qcom,cpulist = <&CPU4 &CPU5 &CPU6>; qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; qcom,target-dev = <&cpu4_llcc_ddr_lat>; qcom,cachemiss-ev = <0x1000>; ddr4-map { Loading @@ -2623,26 +2623,6 @@ }; }; cpu7_llcc_ddr_latmon: qcom,cpu7-llcc-ddr-latmon { compatible = "qcom,arm-memlat-mon"; qcom,cpulist = <&CPU7>; qcom,target-dev = <&cpu4_llcc_ddr_lat>; qcom,cachemiss-ev = <0x1000>; ddr4-map { qcom,ddr-type = <DDR_TYPE_LPDDR4X>; qcom,core-dev-table = < 2361600 MHZ_TO_MBPS( 300, 4) >, < 2707200 MHZ_TO_MBPS(2133, 4) >; }; ddr5-map { qcom,ddr-type = <DDR_TYPE_LPDDR5>; qcom,core-dev-table = < 2361600 MHZ_TO_MBPS( 300, 4) >, < 2707200 MHZ_TO_MBPS(3196, 4) >; }; }; cpu4_computemon: qcom,cpu4-computemon { compatible = "qcom,arm-compute-mon"; qcom,target-dev = <&cpu4_cpu_ddr_latfloor>; Loading