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Commit fc20f0c1 authored by Martin Schwidefsky's avatar Martin Schwidefsky Committed by Heiko Carstens
Browse files

s390/disassembler: update opcode table 



Sync with binutils and add a couple of missing instructions.

Signed-off-by: default avatarMartin Schwidefsky <schwidefsky@de.ibm.com>
Signed-off-by: default avatarHeiko Carstens <heiko.carstens@de.ibm.com>
parent 567b7223

arch/s390/kernel/dis.c

+2 −3
Original line number Diff line number Diff line
@@ -242,6 +242,7 @@ static const unsigned char formats[][6] = { 
	[INSTR_RRF_U0FF]     = { F_24, U4_16, F_28, 0, 0, 0 },

	[INSTR_RRF_U0RF]     = { R_24, U4_16, F_28, 0, 0, 0 },

	[INSTR_RRF_U0RR]     = { R_24, R_28, U4_16, 0, 0, 0 },

	[INSTR_RRF_URR]	     = { R_24, R_28, U8_16, 0, 0, 0 },

	[INSTR_RRF_UUFF]     = { F_24, U4_16, F_28, U4_20, 0, 0 },

	[INSTR_RRF_UUFR]     = { F_24, U4_16, R_28, U4_20, 0, 0 },

	[INSTR_RRF_UURF]     = { R_24, U4_16, F_28, U4_20, 0, 0 },
@@ -306,7 +307,7 @@ static const unsigned char formats[][6] = { 
	[INSTR_VRI_VVV0UU2]  = { V_8, V_12, V_16, U8_28, U4_24, 0 },

	[INSTR_VRR_0V]	     = { V_12, 0, 0, 0, 0, 0 },

	[INSTR_VRR_0VV0U]    = { V_12, V_16, U4_24, 0, 0, 0 },

	[INSTR_VRR_RV0U]     = { R_8, V_12, U4_24, 0, 0, 0 },

	[INSTR_VRR_RV0UU]    = { R_8, V_12, U4_24, U4_28, 0, 0 },

	[INSTR_VRR_VRR]	     = { V_8, R_12, R_16, 0, 0, 0 },

	[INSTR_VRR_VV]	     = { V_8, V_12, 0, 0, 0, 0 },

	[INSTR_VRR_VV0U]     = { V_8, V_12, U4_32, 0, 0, 0 },
@@ -326,10 +327,8 @@ static const unsigned char formats[][6] = { 
	[INSTR_VRS_RVRDU]    = { R_8, V_12, D_20, B_16, U4_32, 0 },

	[INSTR_VRS_VRRD]     = { V_8, R_12, D_20, B_16, 0, 0 },

	[INSTR_VRS_VRRDU]    = { V_8, R_12, D_20, B_16, U4_32, 0 },

	[INSTR_VRS_VVRD]     = { V_8, V_12, D_20, B_16, 0, 0 },

	[INSTR_VRS_VVRDU]    = { V_8, V_12, D_20, B_16, U4_32, 0 },

	[INSTR_VRV_VVXRDU]   = { V_8, D_20, VX_12, B_16, U4_32, 0 },

	[INSTR_VRX_VRRD]     = { V_8, D_20, X_12, B_16, 0, 0 },

	[INSTR_VRX_VRRDU]    = { V_8, D_20, X_12, B_16, U4_32, 0 },

	[INSTR_VRX_VV]	     = { V_8, V_12, 0, 0, 0, 0 },

	[INSTR_VSI_URDV]     = { V_32, D_20, B_16, U8_8, 0, 0 },

arch/s390/tools/opcodes.txt

+44 −7
Original line number Diff line number Diff line
@@ -520,6 +520,9 @@ b92e km RRE_RR 
b92f	kmc	RRE_RR

b930	cgfr	RRE_RR

b931	clgfr	RRE_RR

b938	sortl	RRE_RR

b939	dfltcc	RRF_R0RR2

b93a	kdsa	RRE_RR

b93c	ppno	RRE_RR

b93e	kimd	RRE_RR

b93f	klmd	RRE_RR
@@ -538,8 +541,16 @@ b95a cxlgtr RRF_UUFR 
b95b	cxlftr	RRF_UUFR

b960	cgrt	RRF_U0RR

b961	clgrt	RRF_U0RR

b964	nngrk	RRF_R0RR2

b965	ocgrk	RRF_R0RR2

b966	nogrk	RRF_R0RR2

b967	nxgrk	RRF_R0RR2

b972	crt	RRF_U0RR

b973	clrt	RRF_U0RR

b974	nnrk	RRF_R0RR2

b975	ocrk	RRF_R0RR2

b976	nork	RRF_R0RR2

b977	nxrk	RRF_R0RR2

b980	ngr	RRE_RR

b981	ogr	RRE_RR

b982	xgr	RRE_RR
@@ -573,6 +584,7 @@ b99f ssair RRE_R0 
b9a0	clp	RRF_U0RR

b9a1	tpei	RRE_RR

b9a2	ptf	RRE_R0

b9a4	uvc	RRF_URR

b9aa	lptea	RRF_RURR2

b9ab	essa	RRF_U0RR

b9ac	irbm	RRE_RR
@@ -585,6 +597,7 @@ b9b3 cu42 RRE_RR 
b9bd	trtre	RRF_U0RR

b9be	srstu	RRE_RR

b9bf	trte	RRF_U0RR

b9c0	selhhhr	RRF_RURR

b9c8	ahhhr	RRF_R0RR2

b9c9	shhhr	RRF_R0RR2

b9ca	alhhhr	RRF_R0RR2
@@ -594,6 +607,9 @@ b9cf clhhr RRE_RR 
b9d0	pcistg	RRE_RR

b9d2	pcilg	RRE_RR

b9d3	rpcit	RRE_RR

b9d4	pcistgi	RRE_RR

b9d5	pciwb	RRE_00

b9d6	pcilgi	RRE_RR

b9d8	ahhlr	RRF_R0RR2

b9d9	shhlr	RRF_R0RR2

b9da	alhhlr	RRF_R0RR2
@@ -601,9 +617,11 @@ b9db slhhlr RRF_R0RR2 
b9dd	chlr	RRE_RR

b9df	clhlr	RRE_RR

b9e0	locfhr	RRF_U0RR

b9e1	popcnt	RRE_RR

b9e1	popcnt	RRF_U0RR

b9e2	locgr	RRF_U0RR

b9e3	selgr	RRF_RURR

b9e4	ngrk	RRF_R0RR2

b9e5	ncgrk	RRF_R0RR2

b9e6	ogrk	RRF_R0RR2

b9e7	xgrk	RRF_R0RR2

b9e8	agrk	RRF_R0RR2
@@ -612,8 +630,10 @@ b9ea algrk RRF_R0RR2 
b9eb	slgrk	RRF_R0RR2

b9ec	mgrk	RRF_R0RR2

b9ed	msgrkc	RRF_R0RR2

b9f0	selr	RRF_RURR

b9f2	locr	RRF_U0RR

b9f4	nrk	RRF_R0RR2

b9f5	ncrk	RRF_R0RR2

b9f6	ork	RRF_R0RR2

b9f7	xrk	RRF_R0RR2

b9f8	ark	RRF_R0RR2
@@ -822,6 +842,7 @@ e3d4 stpcifc RXY_RRRD 
e500	lasp	SSE_RDRD

e501	tprot	SSE_RDRD

e502	strag	SSE_RDRD

e50a	mvcrl	SSE_RDRD

e50e	mvcsk	SSE_RDRD

e50f	mvcdk	SSE_RDRD

e544	mvhhi	SIL_RDI
@@ -835,6 +856,18 @@ e55c chsi SIL_RDI 
e55d	clfhsi	SIL_RDU

e560	tbegin	SIL_RDU

e561	tbeginc	SIL_RDU

e601	vlebrh	VRX_VRRDU

e602	vlebrg	VRX_VRRDU

e603	vlebrf	VRX_VRRDU

e604	vllebrz	VRX_VRRDU

e605	vlbrrep	VRX_VRRDU

e606	vlbr	VRX_VRRDU

e607	vler	VRX_VRRDU

e609	vstebrh	VRX_VRRDU

e60a	vstebrg	VRX_VRRDU

e60b	vstebrf	VRX_VRRDU

e60e	vstbr	VRX_VRRDU

e60f	vster	VRX_VRRDU

e634	vpkz	VSI_URDV

e635	vlrl	VSI_URDV

e637	vlrlr	VRS_RRDV
@@ -842,8 +875,8 @@ e63c vupkz VSI_URDV 
e63d	vstrl	VSI_URDV

e63f	vstrlr	VRS_RRDV

e649	vlip	VRI_V0UU2

e650	vcvb	VRR_RV0U

e652	vcvbg	VRR_RV0U

e650	vcvb	VRR_RV0UU

e652	vcvbg	VRR_RV0UU

e658	vcvd	VRI_VR0UU

e659	vsrp	VRI_VVUUU2

e65a	vcvdg	VRI_VR0UU
@@ -863,13 +896,13 @@ e702 vleg VRX_VRRDU 
e703	vlef	VRX_VRRDU

e704	vllez	VRX_VRRDU

e705	vlrep	VRX_VRRDU

e706	vl	VRX_VRRD

e706	vl	VRX_VRRDU

e707	vlbb	VRX_VRRDU

e708	vsteb	VRX_VRRDU

e709	vsteh	VRX_VRRDU

e70a	vsteg	VRX_VRRDU

e70b	vstef	VRX_VRRDU

e70e	vst	VRX_VRRD

e70e	vst	VRX_VRRDU

e712	vgeg	VRV_VVXRDU

e713	vgef	VRV_VVXRDU

e71a	vsceg	VRV_VVXRDU
@@ -879,11 +912,11 @@ e722 vlvg VRS_VRRDU 
e727	lcbb	RXE_RRRDU

e730	vesl	VRS_VVRDU

e733	verll	VRS_VVRDU

e736	vlm	VRS_VVRD

e736	vlm	VRS_VVRDU

e737	vll	VRS_VRRD

e738	vesrl	VRS_VVRDU

e73a	vesra	VRS_VVRDU

e73e	vstm	VRS_VVRD

e73e	vstm	VRS_VVRDU

e73f	vstl	VRS_VRRD

e740	vleib	VRI_V0IU

e741	vleih	VRI_V0IU
@@ -932,7 +965,10 @@ e781 vfene VRR_VVV0U0U 
e782	vfae	VRR_VVV0U0U

e784	vpdi	VRR_VVV0U

e785	vbperm	VRR_VVV

e786	vsld	VRI_VVV0U

e787	vsrd	VRI_VVV0U

e78a	vstrc	VRR_VVVUU0V

e78b	vstrs	VRR_VVVUU0V

e78c	vperm	VRR_VVV0V

e78d	vsel	VRR_VVV0V

e78e	vfms	VRR_VVVU0UV
@@ -1060,6 +1096,7 @@ eb9b stamy RSY_AARD 
ebc0	tp	RSL_R0RD

ebd0	pcistb	RSY_RRRD

ebd1	sic	RSY_RRRD

ebd4	pcistbi	RSY_RRRD

ebdc	srak	RSY_RRRD

ebdd	slak	RSY_RRRD

ebde	srlk	RSY_RRRD