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Commit fc20eeff authored by Mark Zhang's avatar Mark Zhang Committed by Peter De Schrijver
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clk: tegra: Set the clock parent of gr2d/gr3d to pll_c2 



pll_m will be the parent of gr2d/gr3d if we don't do this.
And because pll_m runs at a high rate so gr2d/gr3d will be
unstable. So change the parent of them to pll_c2.

Signed-off-by: default avatarMark Zhang <markz@nvidia.com>
Acked-By: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
parent d17cb95f

drivers/clk/tegra/clk-tegra114.c

+3 −0
Original line number Diff line number Diff line
@@ -2180,6 +2180,9 @@ static struct tegra_clk_init_table init_table[] __initdata = { 
	{TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},

	{TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1},

	{TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1},

	{TEGRA114_CLK_GR_2D, TEGRA114_CLK_PLL_C2, 300000000, 0},

	{TEGRA114_CLK_GR_3D, TEGRA114_CLK_PLL_C2, 300000000, 0},



	/* This MUST be the last entry. */

	{TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0},

};