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Commit fbe6c404 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-fixes-for-linus' of... 

Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip

* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  dmar, x86: Use function stubs when CONFIG_INTR_REMAP is disabled
  x86-64: Fix and clean up AMD Fam10 MMCONF enabling
  x86: UV: Address interrupt/IO port operation conflict
  x86: Use online node real index in calulate_tbl_offset()
  x86, asm: Fix binutils 2.15 build failure
parents d2f30c73 4917b284

arch/x86/include/asm/msr-index.h

+1 −1
Original line number Diff line number Diff line
@@ -128,7 +128,7 @@ 
#define FAM10H_MMIO_CONF_ENABLE		(1<<0)

#define FAM10H_MMIO_CONF_BUSRANGE_MASK	0xf

#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2

#define FAM10H_MMIO_CONF_BASE_MASK	0xfffffff

#define FAM10H_MMIO_CONF_BASE_MASK	0xfffffffULL

#define FAM10H_MMIO_CONF_BASE_SHIFT	20

#define MSR_FAM10H_NODE_ID		0xc001100c

arch/x86/include/asm/uv/uv_hub.h

+4 −0
Original line number Diff line number Diff line
@@ -199,6 +199,8 @@ union uvh_apicid { 
#define UVH_APICID		0x002D0E00L

#define UV_APIC_PNODE_SHIFT	6



#define UV_APICID_HIBIT_MASK	0xffff0000



/* Local Bus from cpu's perspective */

#define LOCAL_BUS_BASE		0x1c00000

#define LOCAL_BUS_SIZE		(4 * 1024 * 1024)
@@ -491,8 +493,10 @@ static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value) 
	}

}



extern unsigned int uv_apicid_hibits;

static unsigned long uv_hub_ipi_value(int apicid, int vector, int mode)

{

	apicid |= uv_apicid_hibits;

	return (1UL << UVH_IPI_INT_SEND_SHFT) |

			((apicid) << UVH_IPI_INT_APIC_ID_SHFT) |

			(mode << UVH_IPI_INT_DELIVERY_MODE_SHFT) |

arch/x86/include/asm/uv/uv_mmrs.h

+18 −1
Original line number Diff line number Diff line
@@ -5,7 +5,7 @@ 
 *

 * SGI UV MMR definitions

 *

 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.

 * Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved.

 */



#ifndef _ASM_X86_UV_UV_MMRS_H
@@ -753,6 +753,23 @@ union uvh_lb_bau_sb_descriptor_base_u { 
    } s;

};



/* ========================================================================= */

/*                   UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK                     */

/* ========================================================================= */

#define UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK 0x320130UL

#define UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK_32 0x009f0



#define UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_SHFT 0

#define UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_MASK 0x00000000ffffffffUL



union uvh_lb_target_physical_apic_id_mask_u {

	unsigned long v;

	struct uvh_lb_target_physical_apic_id_mask_s {

		unsigned long bit_enables : 32;  /* RW */

		unsigned long rsvd_32_63  : 32;  /*    */

	} s;

};



/* ========================================================================= */

/*                               UVH_NODE_ID                                 */

/* ========================================================================= */

arch/x86/kernel/apic/x2apic_uv_x.c

+23 −2
Original line number Diff line number Diff line
@@ -44,6 +44,8 @@ static u64 gru_start_paddr, gru_end_paddr; 
static union uvh_apicid uvh_apicid;

int uv_min_hub_revision_id;

EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);

unsigned int uv_apicid_hibits;

EXPORT_SYMBOL_GPL(uv_apicid_hibits);

static DEFINE_SPINLOCK(uv_nmi_lock);



static inline bool is_GRU_range(u64 start, u64 end)
@@ -85,6 +87,23 @@ static void __init early_get_apic_pnode_shift(void) 
		uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT;

}



/*

 * Add an extra bit as dictated by bios to the destination apicid of

 * interrupts potentially passing through the UV HUB.  This prevents

 * a deadlock between interrupts and IO port operations.

 */

static void __init uv_set_apicid_hibit(void)

{

	union uvh_lb_target_physical_apic_id_mask_u apicid_mask;

	unsigned long *mmr;



	mmr = early_ioremap(UV_LOCAL_MMR_BASE |

		UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK, sizeof(*mmr));

	apicid_mask.v = *mmr;

	early_iounmap(mmr, sizeof(*mmr));

	uv_apicid_hibits = apicid_mask.s.bit_enables & UV_APICID_HIBIT_MASK;

}



static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)

{

	int nodeid;
@@ -102,6 +121,7 @@ static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id) 
			__get_cpu_var(x2apic_extra_bits) =

				nodeid << (uvh_apicid.s.pnode_shift - 1);

			uv_system_type = UV_NON_UNIQUE_APIC;

			uv_set_apicid_hibit();

			return 1;

		}

	}
@@ -155,6 +175,7 @@ static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_ri 
	int pnode;



	pnode = uv_apicid_to_pnode(phys_apicid);

	phys_apicid |= uv_apicid_hibits;

	val = (1UL << UVH_IPI_INT_SEND_SHFT) |

	    (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |

	    ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
@@ -236,7 +257,7 @@ static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask) 
	int cpu = cpumask_first(cpumask);



	if ((unsigned)cpu < nr_cpu_ids)

		return per_cpu(x86_cpu_to_apicid, cpu);

		return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;

	else

		return BAD_APICID;

}
@@ -255,7 +276,7 @@ uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 
		if (cpumask_test_cpu(cpu, cpu_online_mask))

			break;

	}

	return per_cpu(x86_cpu_to_apicid, cpu);

	return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;

}



static unsigned int x2apic_get_apic_id(unsigned long x)

arch/x86/kernel/entry_32.S

+1 −1
Original line number Diff line number Diff line
@@ -395,7 +395,7 @@ sysenter_past_esp: 
	 * A tiny bit of offset fixup is necessary - 4*4 means the 4 words

	 * pushed above; +8 corresponds to copy_thread's esp0 setting.

	 */

	pushl_cfi (TI_sysenter_return-THREAD_SIZE_asm+8+4*4)(%esp)

	pushl_cfi ((TI_sysenter_return)-THREAD_SIZE_asm+8+4*4)(%esp)

	CFI_REL_OFFSET eip, 0



	pushl_cfi %eax