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Commit fbe4a49f authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'stm32-dt-for-v5.4-1' of... 

Merge tag 'stm32-dt-for-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt

STM32 DT updates for v5.4, round 1

Highlights:
----------

MPU part:
 -Add FMC2 NAND controller support on stm32mp157c-ev1.
 -Add M4 remoteproc support:
  -Add support in stm32mp157c.dtsi.
  -Declare copro reserved memories region on stm32mp157 EV1 and DK1
   boards.
  -Enable M4 copro support on stm32mp157 EV1 and DK1.
 -Add booster for ADC on stm32mp157c.
 -Add audio codec support on stm32mp157 DK1.

MCU part:
 -Remove fixed regulator unit address on stm32429i-eval used by ADC.
 -Add missing vdd-supply required by ADC on stm32429i-eval and
  stm32h743i-eval.
 -Add pwm cells on f746 and f429.

* tag 'stm32-dt-for-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (21 commits)
  ARM: dts: stm32: remove useless pinctrl entries in stm32mp157-pinctrl
  ARM: dts: stm32: add phy-dsi-supply property on stm32mp157c-ev1
  ARM: dts: stm32: add audio codec support on stm32mp157a-dk1 board
  ARM: dts: stm32: add syscfg to ADC on stm32mp157c
  ARM: dts: stm32: add pwm cells to stm32f746
  ARM: dts: stm32: add pwm cells to stm32f429
  ARM: dts: stm32: add pwm cells to stm32mp157c
  ARM: dts: stm32: fix -Wall W=1 compilation in stm32mp157 pinctrl for mcan
  ARM: dts: stm32: add booster for ADC analog switches on stm32mp157c
  ARM: dts: stm32: enable m4 coprocessor support on STM32MP157a-dk1
  ARM: dts: stm32: declare copro reserved memories on STM32MP157a-dk1
  ARM: dts: stm32: enable m4 coprocessor support on STM32MP157c-ed1
  ARM: dts: stm32: declare copro reserved memories on STM32MP157c-ed1
  ARM: dts: stm32: add m4 remoteproc support on STM32MP157c
  ARM: dts: stm32: add missing vdda-supply to adc on stm32h743i-eval
  ARM: dts: stm32: add missing vdda-supply to adc on stm32429i-eval
  ARM: dts: stm32: remove fixed regulator unit address on stm32429i-eval
  ARM: dts: stm32: enable FMC2 NAND controller on stm32mp157c-ev1
  ARM: dts: stm32: add FMC2 NAND controller pins muxing on stm32mp157c-ev1
  ARM: dts: stm32: add FMC2 NAND controller support on stm32mp157c
  ...

Link: https://lore.kernel.org/r/482a2a40-a246-6654-7e3b-8e38b137752f@st.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents d1406583 49490d51

arch/arm/boot/dts/stm32429i-eval.dts

+13 −12
Original line number Diff line number Diff line
@@ -81,19 +81,19 @@ 
		dma-ranges = <0xc0000000 0x0 0x10000000>;

	};



	regulators {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <0>;

	vdda: regulator-vdda {

		compatible = "regulator-fixed";

		regulator-name = "vdda";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;

	};



		reg_vref: regulator@0 {

	vref: regulator-vref {

		compatible = "regulator-fixed";

			reg = <0>;

		regulator-name = "vref";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;

	};

	};



	leds {

		compatible = "gpio-leds";
@@ -157,7 +157,8 @@ 
&adc {

	pinctrl-names = "default";

	pinctrl-0 = <&adc3_in8_pin>;

	vref-supply = <&reg_vref>;

	vdda-supply = <&vdda>;

	vref-supply = <&vref>;

	status = "okay";

	adc3: adc@200 {

		st,adc-channels = <8>;

arch/arm/boot/dts/stm32f429.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -112,6 +112,7 @@ 


			pwm {

				compatible = "st,stm32-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};
@@ -141,6 +142,7 @@ 


			pwm {

				compatible = "st,stm32-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};
@@ -170,6 +172,7 @@ 


			pwm {

				compatible = "st,stm32-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};
@@ -198,6 +201,7 @@ 


			pwm {

				compatible = "st,stm32-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};
@@ -267,6 +271,7 @@ 


			pwm {

				compatible = "st,stm32-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};
@@ -288,6 +293,7 @@ 


			pwm {

				compatible = "st,stm32-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};
@@ -303,6 +309,7 @@ 


			pwm {

				compatible = "st,stm32-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};
@@ -448,6 +455,7 @@ 


			pwm {

				compatible = "st,stm32-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};
@@ -469,6 +477,7 @@ 


			pwm {

				compatible = "st,stm32-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};
@@ -602,6 +611,7 @@ 


			pwm {

				compatible = "st,stm32-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};
@@ -623,6 +633,7 @@ 


			pwm {

				compatible = "st,stm32-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};
@@ -638,6 +649,7 @@ 


			pwm {

				compatible = "st,stm32-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};

arch/arm/boot/dts/stm32f746.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -94,6 +94,7 @@ 


			pwm {

				compatible = "st,stm32-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};
@@ -123,6 +124,7 @@ 


			pwm {

				compatible = "st,stm32-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};
@@ -152,6 +154,7 @@ 


			pwm {

				compatible = "st,stm32-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};
@@ -180,6 +183,7 @@ 


			pwm {

				compatible = "st,stm32-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};
@@ -249,6 +253,7 @@ 


			pwm {

				compatible = "st,stm32-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};
@@ -270,6 +275,7 @@ 


			pwm {

				compatible = "st,stm32-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};
@@ -285,6 +291,7 @@ 


			pwm {

				compatible = "st,stm32-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};
@@ -419,6 +426,7 @@ 


			pwm {

				compatible = "st,stm32-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};
@@ -440,6 +448,7 @@ 


			pwm {

				compatible = "st,stm32-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};
@@ -512,6 +521,7 @@ 


			pwm {

				compatible = "st,stm32-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};
@@ -533,6 +543,7 @@ 


			pwm {

				compatible = "st,stm32-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};
@@ -548,6 +559,7 @@ 


			pwm {

				compatible = "st,stm32-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};

arch/arm/boot/dts/stm32h743i-eval.dts

+1 −0
Original line number Diff line number Diff line
@@ -87,6 +87,7 @@ 
};



&adc_12 {

	vdda-supply = <&vdda>;

	vref-supply = <&vdda>;

	status = "okay";

	adc1: adc@0 {

arch/arm/boot/dts/stm32mp157-pinctrl.dtsi

+45 −25
Original line number Diff line number Diff line
@@ -24,8 +24,6 @@ 
				reg = <0x0 0x400>;

				clocks = <&rcc GPIOA>;

				st,bank-name = "GPIOA";

				ngpios = <16>;

				gpio-ranges = <&pinctrl 0 0 16>;

				status = "disabled";

			};
@@ -37,8 +35,6 @@ 
				reg = <0x1000 0x400>;

				clocks = <&rcc GPIOB>;

				st,bank-name = "GPIOB";

				ngpios = <16>;

				gpio-ranges = <&pinctrl 0 16 16>;

				status = "disabled";

			};
@@ -50,8 +46,6 @@ 
				reg = <0x2000 0x400>;

				clocks = <&rcc GPIOC>;

				st,bank-name = "GPIOC";

				ngpios = <16>;

				gpio-ranges = <&pinctrl 0 32 16>;

				status = "disabled";

			};
@@ -63,8 +57,6 @@ 
				reg = <0x3000 0x400>;

				clocks = <&rcc GPIOD>;

				st,bank-name = "GPIOD";

				ngpios = <16>;

				gpio-ranges = <&pinctrl 0 48 16>;

				status = "disabled";

			};
@@ -76,8 +68,6 @@ 
				reg = <0x4000 0x400>;

				clocks = <&rcc GPIOE>;

				st,bank-name = "GPIOE";

				ngpios = <16>;

				gpio-ranges = <&pinctrl 0 64 16>;

				status = "disabled";

			};
@@ -89,8 +79,6 @@ 
				reg = <0x5000 0x400>;

				clocks = <&rcc GPIOF>;

				st,bank-name = "GPIOF";

				ngpios = <16>;

				gpio-ranges = <&pinctrl 0 80 16>;

				status = "disabled";

			};
@@ -102,8 +90,6 @@ 
				reg = <0x6000 0x400>;

				clocks = <&rcc GPIOG>;

				st,bank-name = "GPIOG";

				ngpios = <16>;

				gpio-ranges = <&pinctrl 0 96 16>;

				status = "disabled";

			};
@@ -115,8 +101,6 @@ 
				reg = <0x7000 0x400>;

				clocks = <&rcc GPIOH>;

				st,bank-name = "GPIOH";

				ngpios = <16>;

				gpio-ranges = <&pinctrl 0 112 16>;

				status = "disabled";

			};
@@ -128,8 +112,6 @@ 
				reg = <0x8000 0x400>;

				clocks = <&rcc GPIOI>;

				st,bank-name = "GPIOI";

				ngpios = <16>;

				gpio-ranges = <&pinctrl 0 128 16>;

				status = "disabled";

			};
@@ -141,8 +123,6 @@ 
				reg = <0x9000 0x400>;

				clocks = <&rcc GPIOJ>;

				st,bank-name = "GPIOJ";

				ngpios = <16>;

				gpio-ranges = <&pinctrl 0 144 16>;

				status = "disabled";

			};
@@ -154,8 +134,6 @@ 
				reg = <0xa000 0x400>;

				clocks = <&rcc GPIOK>;

				st,bank-name = "GPIOK";

				ngpios = <8>;

				gpio-ranges = <&pinctrl 0 160 8>;

				status = "disabled";

			};
@@ -276,6 +254,50 @@ 
				};

			};



			fmc_pins_a: fmc-0 {

				pins1 {

					pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */

						 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */

						 <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */

						 <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */

						 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */

						 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */

						 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */

						 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */

						 <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */

						 <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */

						 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */

						 <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */

						 <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */

					bias-disable;

					drive-push-pull;

					slew-rate = <1>;

				};

				pins2 {

					pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */

					bias-pull-up;

				};

			};



			fmc_sleep_pins_a: fmc-sleep-0 {

				pins {

					pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */

						 <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */

						 <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */

						 <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */

						 <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */

						 <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */

						 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */

						 <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */

						 <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */

						 <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */

						 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */

						 <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */

						 <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */

						 <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */

				};

			};



			i2c1_pins_a: i2c1-0 {

				pins {

					pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
@@ -530,7 +552,7 @@ 
				};

			};



			m_can1_sleep_pins_a: m_can1-sleep@0 {

			m_can1_sleep_pins_a: m_can1-sleep-0 {

				pins {

					pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */

						 <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
@@ -849,8 +871,6 @@ 
				clocks = <&rcc GPIOZ>;

				st,bank-name = "GPIOZ";

				st,bank-ioport = <11>;

				ngpios = <8>;

				gpio-ranges = <&pinctrl_z 0 400 8>;

				status = "disabled";

			};