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Commit fbabbd22 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Configure UCHE GMEM base address based on GMEM size"

parents 18b2685b 16ac4605

drivers/gpu/msm/adreno-gpulist.h

+0 −28
Original line number Diff line number Diff line
@@ -27,7 +27,6 @@ static const struct adreno_a3xx_core adreno_gpu_core_a306 = { 
		.features = ADRENO_SOFT_FAULT_DETECT,

		.gpudev = &adreno_a3xx_gpudev,

		.perfcounters = &adreno_a3xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = SZ_128K,

		.bus_width = 0,

		.snapshot_size = 600 * SZ_1K,
@@ -50,7 +49,6 @@ static const struct adreno_a3xx_core adreno_gpu_core_a306a = { 
		.features = ADRENO_SOFT_FAULT_DETECT,

		.gpudev = &adreno_a3xx_gpudev,

		.perfcounters = &adreno_a3xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = SZ_128K,

		.bus_width = 16,

		.snapshot_size = 600 * SZ_1K,
@@ -71,7 +69,6 @@ static const struct adreno_a3xx_core adreno_gpu_core_a304 = { 
		.features = ADRENO_SOFT_FAULT_DETECT,

		.gpudev = &adreno_a3xx_gpudev,

		.perfcounters = &adreno_a3xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = (SZ_64K + SZ_32K),

		.bus_width = 0,

		.snapshot_size = 600 * SZ_1K,
@@ -196,7 +193,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v2 = { 
			ADRENO_CONTENT_PROTECTION,

		.gpudev = &adreno_a5xx_gpudev,

		.perfcounters = &adreno_a5xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.bus_width = 32,

		.snapshot_size = SZ_1M,
@@ -223,7 +219,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v3 = { 
			ADRENO_CONTENT_PROTECTION,

		.gpudev = &adreno_a5xx_gpudev,

		.perfcounters = &adreno_a5xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.bus_width = 32,

		.snapshot_size = SZ_1M,
@@ -290,7 +285,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a505 = { 
		.features = ADRENO_PREEMPTION,

		.gpudev = &adreno_a5xx_gpudev,

		.perfcounters = &adreno_a5xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_8K),

		.bus_width = 16,

		.snapshot_size = SZ_1M,
@@ -310,7 +304,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a506 = { 
			ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,

		.gpudev = &adreno_a5xx_gpudev,

		.perfcounters = &adreno_a5xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_8K),

		.bus_width = 16,

		.snapshot_size = SZ_1M,
@@ -389,7 +382,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a510 = { 
		DEFINE_ADRENO_REV(ADRENO_REV_A510, 5, 1, 0, ANY_ID),

		.gpudev = &adreno_a5xx_gpudev,

		.perfcounters = &adreno_a5xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_256K,

		.bus_width = 16,

		.snapshot_size = SZ_1M,
@@ -515,7 +507,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a540v2 = { 
			ADRENO_GPMU | ADRENO_SPTP_PC,

		.gpudev = &adreno_a5xx_gpudev,

		.perfcounters = &adreno_a5xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.bus_width = 32,

		.snapshot_size = SZ_1M,
@@ -599,7 +590,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a512 = { 
			ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,

		.gpudev = &adreno_a5xx_gpudev,

		.perfcounters = &adreno_a5xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_256K + SZ_16K),

		.bus_width = 32,

		.snapshot_size = SZ_1M,
@@ -619,7 +609,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a508 = { 
			ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,

		.gpudev = &adreno_a5xx_gpudev,

		.perfcounters = &adreno_a5xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_8K),

		.bus_width = 32,

		.snapshot_size = SZ_1M,
@@ -795,7 +784,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a630v2 = { 
			ADRENO_IOCOHERENT | ADRENO_PREEMPTION,

		.gpudev = &adreno_a630_gpudev,

		.perfcounters = &adreno_a630_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.bus_width = 32,

		.snapshot_size = SZ_1M,
@@ -895,7 +883,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a615 = { 
			ADRENO_IOCOHERENT,

		.gpudev = &adreno_a630_gpudev,

		.perfcounters = &adreno_a6xx_legacy_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.bus_width = 32,

		.snapshot_size = 600 * SZ_1K,
@@ -923,7 +910,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a618 = { 
			ADRENO_IOCOHERENT,

		.gpudev = &adreno_a630_gpudev,

		.perfcounters = &adreno_a6xx_legacy_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.bus_width = 32,

		.snapshot_size = SZ_1M,
@@ -951,7 +937,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a619 = { 
			ADRENO_IOCOHERENT,

		.gpudev = &adreno_a630_gpudev,

		.perfcounters = &adreno_a6xx_legacy_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.bus_width = 32,

		.snapshot_size = SZ_2M,
@@ -978,7 +963,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a619_variant = { 
		.features =  ADRENO_PREEMPTION | ADRENO_CONTENT_PROTECTION,

		.gpudev = &adreno_a619_holi_gpudev,

		.perfcounters = &adreno_a6xx_legacy_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.bus_width = 32,

		.snapshot_size = SZ_2M,
@@ -1110,7 +1094,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a620 = { 
			ADRENO_APRIV,

		.gpudev = &adreno_a630_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = SZ_512K,

		.bus_width = 32,

		.snapshot_size = 2 * SZ_1M,
@@ -1201,7 +1184,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a640 = { 
			ADRENO_IFPC | ADRENO_PREEMPTION,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.perfcounters = &adreno_a6xx_legacy_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M, //Verified 1MB

		.bus_width = 32,

		.snapshot_size = 2 * SZ_1M,
@@ -1282,7 +1264,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650 = { 
			ADRENO_IFPC | ADRENO_APRIV,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */

		.bus_width = 32,

		.snapshot_size = 2 * SZ_1M,
@@ -1312,7 +1293,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650v2 = { 
			ADRENO_LM | ADRENO_APRIV,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */

		.bus_width = 32,

		.snapshot_size = 2 * SZ_1M,
@@ -1341,7 +1321,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a680 = { 
			ADRENO_IFPC | ADRENO_PREEMPTION,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.perfcounters = &adreno_a6xx_legacy_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_2M,

		.bus_width = 32,

		.snapshot_size = SZ_2M,
@@ -1419,7 +1398,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a612 = { 
			ADRENO_IFPC,

		.gpudev = &adreno_a6xx_rgmu_gpudev,

		.perfcounters = &adreno_a6xx_legacy_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_4K),

		.bus_width = 32,

		.snapshot_size = SZ_1M,
@@ -1445,7 +1423,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a616 = { 
			ADRENO_IOCOHERENT,

		.gpudev = &adreno_a630_gpudev,

		.perfcounters = &adreno_a6xx_legacy_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.bus_width = 32,

		.snapshot_size = SZ_1M,
@@ -1472,7 +1449,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a610 = { 
			ADRENO_PREEMPTION,

		.gpudev = &adreno_a6xx_gpudev,

		.perfcounters = &adreno_a6xx_legacy_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_4K),

		.bus_width = 32,

	},
@@ -1594,7 +1570,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a660 = { 
				ADRENO_IFPC | ADRENO_PREEMPTION,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = SZ_1M + SZ_512K,

		.bus_width = 32,

		.snapshot_size = SZ_2M,
@@ -1626,7 +1601,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a660v2 = { 
				ADRENO_IFPC | ADRENO_PREEMPTION | ADRENO_ACD,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = SZ_1M + SZ_512K,

		.bus_width = 32,

		.snapshot_size = SZ_2M,
@@ -1659,7 +1633,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a660_shima = { 
				ADRENO_IFPC | ADRENO_PREEMPTION | ADRENO_ACD,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = SZ_1M + SZ_512K,

		.bus_width = 32,

		.snapshot_size = SZ_2M,
@@ -1691,7 +1664,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a635 = { 
				ADRENO_PREEMPTION | ADRENO_IFPC,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = SZ_512K,

		.bus_width = 32,

		.snapshot_size = SZ_2M,

drivers/gpu/msm/adreno.c

+15 −3
Original line number Diff line number Diff line
@@ -1297,6 +1297,18 @@ static void adreno_setup_device(struct adreno_device *adreno_dev) 


		INIT_LIST_HEAD(&rb->events.group);

	}



	/*

	 * Some GPUs needs UCHE GMEM base address to be minimum 0x100000

	 * and 1MB aligned. Configure UCHE GMEM base based on GMEM size

	 * and align it one 1MB. This needs to be done based on GMEM size

	 * because setting it to minimum value 0x100000 will result in RB

	 * and UCHE GMEM range overlap for GPUs with GMEM size >1MB.

	 */

	if (!adreno_is_a650_family(adreno_dev))

		adreno_dev->uche_gmem_base =

			ALIGN(adreno_dev->gpucore->gmem_size, SZ_1M);



}



static const struct of_device_id adreno_gmu_match[] = {
@@ -2238,7 +2250,7 @@ static int adreno_prop_device_info(struct kgsl_device *device, 
		.device_id = device->id + 1,

		.chip_id = adreno_dev->chipid,

		.mmu_enabled = kgsl_mmu_has_feature(device, KGSL_MMU_PAGED),

		.gmem_gpubaseaddr = adreno_dev->gpucore->gmem_base,

		.gmem_gpubaseaddr = 0,

		.gmem_sizebytes = adreno_dev->gpucore->gmem_size,

	};
@@ -2305,9 +2317,9 @@ static int adreno_prop_uche_gmem_addr(struct kgsl_device *device, 
		struct kgsl_device_getproperty *param)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	u64 vaddr = adreno_dev->gpucore->gmem_base;



	return copy_prop(param, &vaddr, sizeof(vaddr));

	return copy_prop(param, &adreno_dev->uche_gmem_base,

		sizeof(adreno_dev->uche_gmem_base));

}



static int adreno_prop_ucode_version(struct kgsl_device *device,

drivers/gpu/msm/adreno.h

+2 −2
Original line number Diff line number Diff line
@@ -378,7 +378,6 @@ struct adreno_power_ops { 
 * @patchid: Match for the patch revision of the GPU

 * @features: Common adreno features supported by this core

 * @gpudev: Pointer to the GPU family specific functions for this core

 * @gmem_base: Base address of binning memory (GMEM/OCMEM)

 * @gmem_size: Amount of binning memory (GMEM/OCMEM) to reserve for the core

 * @bus_width: Bytes transferred in 1 cycle

 */
@@ -393,7 +392,6 @@ struct adreno_gpu_core { 
	unsigned long features;

	const struct adreno_gpudev *gpudev;

	const struct adreno_perfcounters *perfcounters;

	unsigned long gmem_base;

	size_t gmem_size;

	u32 bus_width;

	/** @snapshot_size: Size of the static snapshot region in bytes */
@@ -405,6 +403,7 @@ struct adreno_gpu_core { 
 * @dev: Reference to struct kgsl_device

 * @priv: Holds the private flags specific to the adreno_device

 * @chipid: Chip ID specific to the GPU

 * @uche_gmem_base: Base address of GMEM for UCHE access

 * @cx_misc_len: Length of the CX MISC register block

 * @cx_misc_virt: Pointer where the CX MISC block is mapped

 * @isense_base: Base physical address of isense block
@@ -481,6 +480,7 @@ struct adreno_device { 
	struct kgsl_device dev;    /* Must be first field in this struct */

	unsigned long priv;

	unsigned int chipid;

	u64 uche_gmem_base;

	unsigned long cx_dbgc_base;

	unsigned int cx_dbgc_len;

	void __iomem *cx_dbgc_virt;

drivers/gpu/msm/adreno_a5xx.c

+3 −3
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.

 */



#include <linux/clk/qcom.h>
@@ -1430,10 +1430,10 @@ static void a5xx_start(struct adreno_device *adreno_dev) 


	/* Program the GMEM VA range for the UCHE path */

	kgsl_regwrite(device, A5XX_UCHE_GMEM_RANGE_MIN_LO,

			adreno_dev->gpucore->gmem_base);

			adreno_dev->uche_gmem_base);

	kgsl_regwrite(device, A5XX_UCHE_GMEM_RANGE_MIN_HI, 0x0);

	kgsl_regwrite(device, A5XX_UCHE_GMEM_RANGE_MAX_LO,

			adreno_dev->gpucore->gmem_base +

			adreno_dev->uche_gmem_base +

			adreno_dev->gpucore->gmem_size - 1);

	kgsl_regwrite(device, A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x0);

drivers/gpu/msm/adreno_a6xx.c

+6 −6
Original line number Diff line number Diff line
@@ -562,16 +562,16 @@ void a6xx_start(struct adreno_device *adreno_dev) 
	kgsl_regwrite(device, A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff);



	/*

	 * Some A6xx targets no longer use a programmed GMEM base address

	 * so only write the registers if a non zero address is given

	 * in the GPU list

	 * Some A6xx targets no longer use a programmed UCHE GMEM base

	 * address so only write the registers if this address is

	 * non zero.

	 */

	if (adreno_dev->gpucore->gmem_base) {

	if (adreno_dev->uche_gmem_base) {

		kgsl_regwrite(device, A6XX_UCHE_GMEM_RANGE_MIN_LO,

				adreno_dev->gpucore->gmem_base);

				adreno_dev->uche_gmem_base);

		kgsl_regwrite(device, A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x0);

		kgsl_regwrite(device, A6XX_UCHE_GMEM_RANGE_MAX_LO,

				adreno_dev->gpucore->gmem_base +

				adreno_dev->uche_gmem_base +

				adreno_dev->gpucore->gmem_size - 1);

		kgsl_regwrite(device, A6XX_UCHE_GMEM_RANGE_MAX_HI, 0x0);

	}