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Commit fb6dda83 authored by Long Cheng's avatar Long Cheng Committed by Vinod Koul
Browse files

dt-bindings: dma: uart: rename binding 



The filename matches mtk-uart-apdma.c.
So using "mtk-uart-apdma.txt" should be better.
And add some property.

Signed-off-by: default avatarLong Cheng <long.cheng@mediatek.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 9135408c

Documentation/devicetree/bindings/dma/8250_mtk_dma.txt→Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt

+54 −0
Original line number Diff line number Diff line
@@ -8,26 +8,47 @@ Required properties: 
- reg: The base address of the APDMA register bank.



- interrupts: A single interrupt specifier.

 One interrupt per dma-requests, or 8 if no dma-requests property is present



- dma-requests: The number of DMA channels



- clocks : Must contain an entry for each entry in clock-names.

  See ../clocks/clock-bindings.txt for details.

- clock-names: The APDMA clock for register accesses



- mediatek,dma-33bits: Present if the DMA requires support



Examples:



	apdma: dma-controller@11000380 {

	apdma: dma-controller@11000400 {

		compatible = "mediatek,mt2712-uart-dma";

		reg = <0 0x11000380 0 0x400>;

		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 65 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 66 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 69 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;

		reg = <0 0x11000400 0 0x80>,

		      <0 0x11000480 0 0x80>,

		      <0 0x11000500 0 0x80>,

		      <0 0x11000580 0 0x80>,

		      <0 0x11000600 0 0x80>,

		      <0 0x11000680 0 0x80>,

		      <0 0x11000700 0 0x80>,

		      <0 0x11000780 0 0x80>,

		      <0 0x11000800 0 0x80>,

		      <0 0x11000880 0 0x80>,

		      <0 0x11000900 0 0x80>,

		      <0 0x11000980 0 0x80>;

		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;

		dma-requests = <12>;

		clocks = <&pericfg CLK_PERI_AP_DMA>;

		clock-names = "apdma";

		mediatek,dma-33bits;

		#dma-cells = <1>;

	};