pci: msm: Add support to handle DRV power collapse

Some endpoints require to prevent DRV processor power
collapse in order to meet the latency requirement to
access DDR over PCIe link. Send the vote info over rpmsg
by handling MSM_PCIE_DRV_PC_CTRL request via msm_pcie_pm_control.
Vote info is cached to handle DRV subsystem restart in order to
re-send the current vote info received from request.

Change-Id: If2d4b2211fe55f70f709bf9d7a1e0daca4e0b990
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>