Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit faef8749 authored by Kim Phillips's avatar Kim Phillips Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events amd: Add L3 cache events for Family 17h 

Allow users to symbolically specify L3 events for Family 17h processors
using the existing AMD Uncore driver.

Source of events descriptions are from section 2.1.15.4.1 "L3 Cache PMC
Events" of the latest Family 17h PPR, available here:

  https://www.amd.com/system/files/TechDocs/55570-B1_PUB.zip



Opnly BriefDescriptions added, since they show with and without
the -v and --details flags.

Tested with:

 # perf stat -e l3_request_g1.caching_l3_cache_accesses,amd_l3/event=0x01,umask=0x80/,l3_comb_clstr_state.request_miss,amd_l3/event=0x06,umask=0x01/ perf bench mem memcpy -s 4mb -l 100 -f default
...
         7,006,831      l3_request_g1.caching_l3_cache_accesses
         7,006,830      amd_l3/event=0x01,umask=0x80/
           366,530      l3_comb_clstr_state.request_miss
           366,568      amd_l3/event=0x06,umask=0x01/

Signed-off-by: default avatarKim Phillips <kim.phillips@amd.com>
Reviewed-by: default avatarAndi Kleen <ak@linux.intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Janakarajan Natarajan <janakarajan.natarajan@amd.com>
Cc: Jin Yao <yao.jin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Luke Mujica <lukemujica@google.com>
Cc: Martin Liška <mliska@suse.cz>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lore.kernel.org/lkml/20190919204306.12598-1-kim.phillips@amd.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent c8b567c8

tools/perf/pmu-events/arch/x86/amdfam17h/cache.json

+42 −0
Original line number Diff line number Diff line
@@ -283,5 +283,47 @@ 
    "BriefDescription": "Total cycles spent with one or more fill requests in flight from L2.",

    "PublicDescription": "Total cycles spent with one or more fill requests in flight from L2.",

    "UMask": "0x1"

  },

  {

    "EventName": "l3_request_g1.caching_l3_cache_accesses",

    "EventCode": "0x01",

    "BriefDescription": "Caching: L3 cache accesses",

    "UMask": "0x80",

    "Unit": "L3PMC"

  },

  {

    "EventName": "l3_lookup_state.all_l3_req_typs",

    "EventCode": "0x04",

    "BriefDescription": "All L3 Request Types",

    "UMask": "0xff",

    "Unit": "L3PMC"

  },

  {

    "EventName": "l3_comb_clstr_state.other_l3_miss_typs",

    "EventCode": "0x06",

    "BriefDescription": "Other L3 Miss Request Types",

    "UMask": "0xfe",

    "Unit": "L3PMC"

  },

  {

    "EventName": "l3_comb_clstr_state.request_miss",

    "EventCode": "0x06",

    "BriefDescription": "L3 cache misses",

    "UMask": "0x01",

    "Unit": "L3PMC"

  },

  {

    "EventName": "xi_sys_fill_latency",

    "EventCode": "0x90",

    "BriefDescription": "L3 Cache Miss Latency. Total cycles for all transactions divided by 16. Ignores SliceMask and ThreadMask.",

    "UMask": "0x00",

    "Unit": "L3PMC"

  },

  {

    "EventName": "xi_ccx_sdp_req1.all_l3_miss_req_typs",

    "EventCode": "0x9a",

    "BriefDescription": "All L3 Miss Request Types. Ignores SliceMask and ThreadMask.",

    "UMask": "0x3f",

    "Unit": "L3PMC"

  }

]

tools/perf/pmu-events/jevents.c

+1 −0
Original line number Diff line number Diff line
@@ -239,6 +239,7 @@ static struct map { 
	{ "hisi_sccl,ddrc", "hisi_sccl,ddrc" },

	{ "hisi_sccl,hha", "hisi_sccl,hha" },

	{ "hisi_sccl,l3c", "hisi_sccl,l3c" },

	{ "L3PMC", "amd_l3" },

	{}

};