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Commit fad9fab9 authored by Thor Thayer's avatar Thor Thayer Committed by Borislav Petkov
Browse files

EDAC/altera, firmware/intel: Add Stratix10 ECC DBE SMC call 



Reserve ECC Double Bit Error SMC call to alert U-Boot that a DBE has
occurred. Move the call from local EDAC header file to a common header.

 [ bp: Merge the two patches. ]

Signed-off-by: default avatarThor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Reviewed-by: default avatarRichard Gong <richard.gong@intel.com>
Reviewed-by: Alan Tull <atull@kernel.org> # firmware
Cc: Greg KH <greg@kroah.com>
Cc: James Morse <james.morse@arm.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: mchehab@kernel.org
Link: https://lkml.kernel.org/r/1553870639-23895-1-git-send-email-thor.thayer@linux.intel.com



Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
parent 788586ef

drivers/edac/altera_edac.c

+1 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
#include <linux/ctype.h>

#include <linux/delay.h>

#include <linux/edac.h>

#include <linux/firmware/intel/stratix10-smc.h>

#include <linux/genalloc.h>

#include <linux/interrupt.h>

#include <linux/irqchip/chained_irq.h>

drivers/edac/altera_edac.h

+0 −83
Original line number Diff line number Diff line
@@ -372,87 +372,4 @@ struct altr_arria10_edac { 
	struct notifier_block	panic_notifier;

};



/*

 * Functions specified by ARM SMC Calling convention:

 *

 * FAST call executes atomic operations, returns when the requested operation

 * has completed.

 * STD call starts a operation which can be preempted by a non-secure

 * interrupt. The call can return before the requested operation has

 * completed.

 *

 * a0..a7 is used as register names in the descriptions below, on arm32

 * that translates to r0..r7 and on arm64 to w0..w7.

 */



#define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \

	ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \

	ARM_SMCCC_OWNER_SIP, (func_num))



#define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \

	ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \

	ARM_SMCCC_OWNER_SIP, (func_num))



#define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION		0xFFFFFFFF

#define INTEL_SIP_SMC_STATUS_OK				0x0

#define INTEL_SIP_SMC_REG_ERROR				0x5



/*

 * Request INTEL_SIP_SMC_REG_READ

 *

 * Read a protected register using SMCCC

 *

 * Call register usage:

 * a0: INTEL_SIP_SMC_REG_READ.

 * a1: register address.

 * a2-7: not used.

 *

 * Return status:

 * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_REG_ERROR, or

 *     INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION

 * a1: Value in the register

 * a2-3: not used.

 */

#define INTEL_SIP_SMC_FUNCID_REG_READ 7

#define INTEL_SIP_SMC_REG_READ \

	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_READ)



/*

 * Request INTEL_SIP_SMC_REG_WRITE

 *

 * Write a protected register using SMCCC

 *

 * Call register usage:

 * a0: INTEL_SIP_SMC_REG_WRITE.

 * a1: register address

 * a2: value to program into register.

 * a3-7: not used.

 *

 * Return status:

 * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_REG_ERROR, or

 *     INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION

 * a1-3: not used.

 */

#define INTEL_SIP_SMC_FUNCID_REG_WRITE 8

#define INTEL_SIP_SMC_REG_WRITE \

	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_WRITE)



/*

 * Request INTEL_SIP_SMC_ECC_DBE

 *

 * Sync call used by service driver at EL1 alert EL3 that a Double Bit

 * ECC error has occurred.

 *

 * Call register usage:

 * a0 INTEL_SIP_SMC_ECC_DBE

 * a1 SysManager Double Bit Error value

 * a2-7 not used

 *

 * Return status

 * a0 INTEL_SIP_SMC_STATUS_OK

 */

#define INTEL_SIP_SMC_FUNCID_ECC_DBE 13

#define INTEL_SIP_SMC_ECC_DBE \

	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_ECC_DBE)



#endif	/* #ifndef _ALTERA_EDAC_H */

include/linux/firmware/intel/stratix10-smc.h

+19 −0
Original line number Diff line number Diff line
@@ -309,4 +309,23 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) 
#define INTEL_SIP_SMC_FUNCID_RSU_UPDATE 12

#define INTEL_SIP_SMC_RSU_UPDATE \

	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_UPDATE)



/*

 * Request INTEL_SIP_SMC_ECC_DBE

 *

 * Sync call used by service driver at EL1 to alert EL3 that a Double

 * Bit ECC error has occurred.

 *

 * Call register usage:

 * a0 INTEL_SIP_SMC_ECC_DBE

 * a1 SysManager Double Bit Error value

 * a2-7 not used

 *

 * Return status

 * a0 INTEL_SIP_SMC_STATUS_OK

 */

#define INTEL_SIP_SMC_FUNCID_ECC_DBE 13

#define INTEL_SIP_SMC_ECC_DBE \

	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_ECC_DBE)



#endif