Loading qcom/shima-pcie.dtsi +1 −10 Original line number Original line Diff line number Diff line Loading @@ -33,7 +33,7 @@ 0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; msi-parent = <&pcie0_msi_snps>; msi-parent = <&pcie0_msi>; perst-gpio = <&tlmm 94 0>; perst-gpio = <&tlmm 94 0>; wake-gpio = <&tlmm 96 0>; wake-gpio = <&tlmm 96 0>; Loading Loading @@ -194,15 +194,6 @@ }; }; }; }; pcie0_msi_snps: qcom,pcie0_msi@a0000000 { compatible = "qcom,pci-msi"; msi-controller; reg = <0xa0000000 0x0>; interrupt-parent = <&intc>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; qcom,snps; }; pcie0_msi: qcom,pcie0_msi@17a10040 { pcie0_msi: qcom,pcie0_msi@17a10040 { compatible = "qcom,pci-msi"; compatible = "qcom,pci-msi"; msi-controller; msi-controller; Loading Loading
qcom/shima-pcie.dtsi +1 −10 Original line number Original line Diff line number Diff line Loading @@ -33,7 +33,7 @@ 0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; msi-parent = <&pcie0_msi_snps>; msi-parent = <&pcie0_msi>; perst-gpio = <&tlmm 94 0>; perst-gpio = <&tlmm 94 0>; wake-gpio = <&tlmm 96 0>; wake-gpio = <&tlmm 96 0>; Loading Loading @@ -194,15 +194,6 @@ }; }; }; }; pcie0_msi_snps: qcom,pcie0_msi@a0000000 { compatible = "qcom,pci-msi"; msi-controller; reg = <0xa0000000 0x0>; interrupt-parent = <&intc>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; qcom,snps; }; pcie0_msi: qcom,pcie0_msi@17a10040 { pcie0_msi: qcom,pcie0_msi@17a10040 { compatible = "qcom,pci-msi"; compatible = "qcom,pci-msi"; msi-controller; msi-controller; Loading