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Commit f9a23481 authored by Neil Armstrong's avatar Neil Armstrong
Browse files

drm/meson: Support Overlay plane for video rendering 



The Amlogic Meson GX SoCs support an Overlay plane behind the primary
plane for video rendering.

This Overlay plane support various YUV layouts :
- YUYV
- NV12 / NV21
- YUV444 / 422 / 420 / 411 / 410

The scaler supports a wide range of scaling ratios, but for simplicity,
plane atomic check limits the scaling from x5 to /5 in vertical and
horizontal scaling.

The z-order is fixed and always behind the primary plane and cannot be changed.

The scaling parameter algorithm was taken from the Amlogic vendor kernel
code and rewritten to match the atomic universal plane requirements.

The video rendering using this overlay plane support has been tested using
the new Kodi DRM-KMS Prime rendering path along the in-review V4L2 Mem2Mem
Hardware Video Decoder up to 3840x2160 NV12 frames on various display modes.

Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Acked-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Tested-by: default avatarMaxime Jourdan <mjourdan@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1541497202-20570-2-git-send-email-narmstrong@baylibre.com
parent 9ef60bd6

drivers/gpu/drm/meson/Makefile

+1 −1
Original line number Diff line number Diff line 
meson-drm-y := meson_drv.o meson_plane.o meson_crtc.o meson_venc_cvbs.o

meson-drm-y += meson_viu.o meson_vpp.o meson_venc.o meson_vclk.o meson_canvas.o

meson-drm-y += meson_viu.o meson_vpp.o meson_venc.o meson_vclk.o meson_canvas.o meson_overlay.o



obj-$(CONFIG_DRM_MESON) += meson-drm.o

obj-$(CONFIG_DRM_MESON_DW_HDMI) += meson_dw_hdmi.o

drivers/gpu/drm/meson/meson_canvas.c

+5 −2
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ 
#define CANVAS_WIDTH_HBIT       0

#define CANVAS_HEIGHT_BIT       9

#define CANVAS_BLKMODE_BIT      24

#define CANVAS_ENDIAN_BIT	26

#define DMC_CAV_LUT_ADDR	0x50 /* 0x14 offset in data sheet */

#define CANVAS_LUT_WR_EN        (0x2 << 8)

#define CANVAS_LUT_RD_EN        (0x1 << 8)
@@ -47,7 +48,8 @@ void meson_canvas_setup(struct meson_drm *priv, 
			uint32_t canvas_index, uint32_t addr,

			uint32_t stride, uint32_t height,

			unsigned int wrap,

			unsigned int blkmode)

			unsigned int blkmode,

			unsigned int endian)

{

	unsigned int val;
@@ -60,7 +62,8 @@ void meson_canvas_setup(struct meson_drm *priv, 
						CANVAS_WIDTH_HBIT) |

		(height << CANVAS_HEIGHT_BIT) |

		(wrap << 22) |

		(blkmode << CANVAS_BLKMODE_BIT));

		(blkmode << CANVAS_BLKMODE_BIT) |

		(endian << CANVAS_ENDIAN_BIT));



	regmap_write(priv->dmc, DMC_CAV_LUT_ADDR,

			CANVAS_LUT_WR_EN | canvas_index);

drivers/gpu/drm/meson/meson_canvas.h

+10 −1
Original line number Diff line number Diff line
@@ -23,6 +23,9 @@ 
#define __MESON_CANVAS_H



#define MESON_CANVAS_ID_OSD1	0x4e

#define MESON_CANVAS_ID_VD1_0	0x60

#define MESON_CANVAS_ID_VD1_1	0x61

#define MESON_CANVAS_ID_VD1_2	0x62



/* Canvas configuration. */

#define MESON_CANVAS_WRAP_NONE	0x00
@@ -33,10 +36,16 @@ 
#define	MESON_CANVAS_BLKMODE_32x32	0x01

#define	MESON_CANVAS_BLKMODE_64x64	0x02



#define MESON_CANVAS_ENDIAN_SWAP16	0x1

#define MESON_CANVAS_ENDIAN_SWAP32	0x3

#define MESON_CANVAS_ENDIAN_SWAP64	0x7

#define MESON_CANVAS_ENDIAN_SWAP128	0xf



void meson_canvas_setup(struct meson_drm *priv,

			uint32_t canvas_index, uint32_t addr,

			uint32_t stride, uint32_t height,

			unsigned int wrap,

			unsigned int blkmode);

			unsigned int blkmode,

			unsigned int endian);



#endif /* __MESON_CANVAS_H */

drivers/gpu/drm/meson/meson_crtc.c

+214 −2
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 
#include <linux/module.h>

#include <linux/mutex.h>

#include <linux/platform_device.h>

#include <linux/bitfield.h>

#include <drm/drmP.h>

#include <drm/drm_atomic.h>

#include <drm/drm_atomic_helper.h>
@@ -98,6 +99,10 @@ static void meson_crtc_atomic_enable(struct drm_crtc *crtc, 
	writel(crtc_state->mode.hdisplay,

	       priv->io_base + _REG(VPP_POSTBLEND_H_SIZE));



	/* VD1 Preblend vertical start/end */

	writel(FIELD_PREP(GENMASK(11, 0), 2303),

			priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END));



	writel_bits_relaxed(VPP_POSTBLEND_ENABLE, VPP_POSTBLEND_ENABLE,

			    priv->io_base + _REG(VPP_MISC));
@@ -110,11 +115,17 @@ static void meson_crtc_atomic_disable(struct drm_crtc *crtc, 
	struct meson_crtc *meson_crtc = to_meson_crtc(crtc);

	struct meson_drm *priv = meson_crtc->priv;



	DRM_DEBUG_DRIVER("\n");



	priv->viu.osd1_enabled = false;

	priv->viu.osd1_commit = false;



	priv->viu.vd1_enabled = false;

	priv->viu.vd1_commit = false;



	/* Disable VPP Postblend */

	writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0,

	writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_VD1_POSTBLEND |

			    VPP_VD1_PREBLEND | VPP_POSTBLEND_ENABLE, 0,

			    priv->io_base + _REG(VPP_MISC));



	if (crtc->state->event && !crtc->state->active) {
@@ -149,6 +160,7 @@ static void meson_crtc_atomic_flush(struct drm_crtc *crtc, 
	struct meson_drm *priv = meson_crtc->priv;



	priv->viu.osd1_commit = true;

	priv->viu.vd1_commit = true;

}



static const struct drm_crtc_helper_funcs meson_crtc_helper_funcs = {
@@ -202,7 +214,7 @@ void meson_crtc_irq(struct meson_drm *priv) 
			meson_canvas_setup(priv, MESON_CANVAS_ID_OSD1,

				priv->viu.osd1_addr, priv->viu.osd1_stride,

				priv->viu.osd1_height, MESON_CANVAS_WRAP_NONE,

				MESON_CANVAS_BLKMODE_LINEAR);

				MESON_CANVAS_BLKMODE_LINEAR, 0);



		/* Enable OSD1 */

		writel_bits_relaxed(VPP_OSD1_POSTBLEND, VPP_OSD1_POSTBLEND,
@@ -211,6 +223,206 @@ void meson_crtc_irq(struct meson_drm *priv) 
		priv->viu.osd1_commit = false;

	}



	/* Update the VD1 registers */

	if (priv->viu.vd1_enabled && priv->viu.vd1_commit) {



		switch (priv->viu.vd1_planes) {

		case 3:

			if (priv->canvas)

				meson_canvas_config(priv->canvas,

						    priv->canvas_id_vd1_2,

						    priv->viu.vd1_addr2,

						    priv->viu.vd1_stride2,

						    priv->viu.vd1_height2,

						    MESON_CANVAS_WRAP_NONE,

						    MESON_CANVAS_BLKMODE_LINEAR,

						    MESON_CANVAS_ENDIAN_SWAP64);

			else

				meson_canvas_setup(priv, MESON_CANVAS_ID_VD1_2,

						   priv->viu.vd1_addr2,

						   priv->viu.vd1_stride2,

						   priv->viu.vd1_height2,

						   MESON_CANVAS_WRAP_NONE,

						   MESON_CANVAS_BLKMODE_LINEAR,

						   MESON_CANVAS_ENDIAN_SWAP64);

		/* fallthrough */

		case 2:

			if (priv->canvas)

				meson_canvas_config(priv->canvas,

						    priv->canvas_id_vd1_1,

						    priv->viu.vd1_addr1,

						    priv->viu.vd1_stride1,

						    priv->viu.vd1_height1,

						    MESON_CANVAS_WRAP_NONE,

						    MESON_CANVAS_BLKMODE_LINEAR,

						    MESON_CANVAS_ENDIAN_SWAP64);

			else

				meson_canvas_setup(priv, MESON_CANVAS_ID_VD1_1,

						   priv->viu.vd1_addr2,

						   priv->viu.vd1_stride2,

						   priv->viu.vd1_height2,

						   MESON_CANVAS_WRAP_NONE,

						   MESON_CANVAS_BLKMODE_LINEAR,

						   MESON_CANVAS_ENDIAN_SWAP64);

		/* fallthrough */

		case 1:

			if (priv->canvas)

				meson_canvas_config(priv->canvas,

						    priv->canvas_id_vd1_0,

						    priv->viu.vd1_addr0,

						    priv->viu.vd1_stride0,

						    priv->viu.vd1_height0,

						    MESON_CANVAS_WRAP_NONE,

						    MESON_CANVAS_BLKMODE_LINEAR,

						    MESON_CANVAS_ENDIAN_SWAP64);

			else

				meson_canvas_setup(priv, MESON_CANVAS_ID_VD1_0,

						   priv->viu.vd1_addr2,

						   priv->viu.vd1_stride2,

						   priv->viu.vd1_height2,

						   MESON_CANVAS_WRAP_NONE,

						   MESON_CANVAS_BLKMODE_LINEAR,

						   MESON_CANVAS_ENDIAN_SWAP64);

		};



		writel_relaxed(priv->viu.vd1_if0_gen_reg,

				priv->io_base + _REG(VD1_IF0_GEN_REG));

		writel_relaxed(priv->viu.vd1_if0_gen_reg,

				priv->io_base + _REG(VD2_IF0_GEN_REG));

		writel_relaxed(priv->viu.vd1_if0_gen_reg2,

				priv->io_base + _REG(VD1_IF0_GEN_REG2));

		writel_relaxed(priv->viu.viu_vd1_fmt_ctrl,

				priv->io_base + _REG(VIU_VD1_FMT_CTRL));

		writel_relaxed(priv->viu.viu_vd1_fmt_ctrl,

				priv->io_base + _REG(VIU_VD2_FMT_CTRL));

		writel_relaxed(priv->viu.viu_vd1_fmt_w,

				priv->io_base + _REG(VIU_VD1_FMT_W));

		writel_relaxed(priv->viu.viu_vd1_fmt_w,

				priv->io_base + _REG(VIU_VD2_FMT_W));

		writel_relaxed(priv->viu.vd1_if0_canvas0,

				priv->io_base + _REG(VD1_IF0_CANVAS0));

		writel_relaxed(priv->viu.vd1_if0_canvas0,

				priv->io_base + _REG(VD1_IF0_CANVAS1));

		writel_relaxed(priv->viu.vd1_if0_canvas0,

				priv->io_base + _REG(VD2_IF0_CANVAS0));

		writel_relaxed(priv->viu.vd1_if0_canvas0,

				priv->io_base + _REG(VD2_IF0_CANVAS1));

		writel_relaxed(priv->viu.vd1_if0_luma_x0,

				priv->io_base + _REG(VD1_IF0_LUMA_X0));

		writel_relaxed(priv->viu.vd1_if0_luma_x0,

				priv->io_base + _REG(VD1_IF0_LUMA_X1));

		writel_relaxed(priv->viu.vd1_if0_luma_x0,

				priv->io_base + _REG(VD2_IF0_LUMA_X0));

		writel_relaxed(priv->viu.vd1_if0_luma_x0,

				priv->io_base + _REG(VD2_IF0_LUMA_X1));

		writel_relaxed(priv->viu.vd1_if0_luma_y0,

				priv->io_base + _REG(VD1_IF0_LUMA_Y0));

		writel_relaxed(priv->viu.vd1_if0_luma_y0,

				priv->io_base + _REG(VD1_IF0_LUMA_Y1));

		writel_relaxed(priv->viu.vd1_if0_luma_y0,

				priv->io_base + _REG(VD2_IF0_LUMA_Y0));

		writel_relaxed(priv->viu.vd1_if0_luma_y0,

				priv->io_base + _REG(VD2_IF0_LUMA_Y1));

		writel_relaxed(priv->viu.vd1_if0_chroma_x0,

				priv->io_base + _REG(VD1_IF0_CHROMA_X0));

		writel_relaxed(priv->viu.vd1_if0_chroma_x0,

				priv->io_base + _REG(VD1_IF0_CHROMA_X1));

		writel_relaxed(priv->viu.vd1_if0_chroma_x0,

				priv->io_base + _REG(VD2_IF0_CHROMA_X0));

		writel_relaxed(priv->viu.vd1_if0_chroma_x0,

				priv->io_base + _REG(VD2_IF0_CHROMA_X1));

		writel_relaxed(priv->viu.vd1_if0_chroma_y0,

				priv->io_base + _REG(VD1_IF0_CHROMA_Y0));

		writel_relaxed(priv->viu.vd1_if0_chroma_y0,

				priv->io_base + _REG(VD1_IF0_CHROMA_Y1));

		writel_relaxed(priv->viu.vd1_if0_chroma_y0,

				priv->io_base + _REG(VD2_IF0_CHROMA_Y0));

		writel_relaxed(priv->viu.vd1_if0_chroma_y0,

				priv->io_base + _REG(VD2_IF0_CHROMA_Y1));

		writel_relaxed(priv->viu.vd1_if0_repeat_loop,

				priv->io_base + _REG(VD1_IF0_RPT_LOOP));

		writel_relaxed(priv->viu.vd1_if0_repeat_loop,

				priv->io_base + _REG(VD2_IF0_RPT_LOOP));

		writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,

				priv->io_base + _REG(VD1_IF0_LUMA0_RPT_PAT));

		writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,

				priv->io_base + _REG(VD2_IF0_LUMA0_RPT_PAT));

		writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,

				priv->io_base + _REG(VD1_IF0_LUMA1_RPT_PAT));

		writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,

				priv->io_base + _REG(VD2_IF0_LUMA1_RPT_PAT));

		writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,

				priv->io_base + _REG(VD1_IF0_CHROMA0_RPT_PAT));

		writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,

				priv->io_base + _REG(VD2_IF0_CHROMA0_RPT_PAT));

		writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,

				priv->io_base + _REG(VD1_IF0_CHROMA1_RPT_PAT));

		writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,

				priv->io_base + _REG(VD2_IF0_CHROMA1_RPT_PAT));

		writel_relaxed(0, priv->io_base + _REG(VD1_IF0_LUMA_PSEL));

		writel_relaxed(0, priv->io_base + _REG(VD1_IF0_CHROMA_PSEL));

		writel_relaxed(0, priv->io_base + _REG(VD2_IF0_LUMA_PSEL));

		writel_relaxed(0, priv->io_base + _REG(VD2_IF0_CHROMA_PSEL));

		writel_relaxed(priv->viu.vd1_range_map_y,

				priv->io_base + _REG(VD1_IF0_RANGE_MAP_Y));

		writel_relaxed(priv->viu.vd1_range_map_cb,

				priv->io_base + _REG(VD1_IF0_RANGE_MAP_CB));

		writel_relaxed(priv->viu.vd1_range_map_cr,

				priv->io_base + _REG(VD1_IF0_RANGE_MAP_CR));

		writel_relaxed(0x78404,

				priv->io_base + _REG(VPP_SC_MISC));

		writel_relaxed(priv->viu.vpp_pic_in_height,

				priv->io_base + _REG(VPP_PIC_IN_HEIGHT));

		writel_relaxed(priv->viu.vpp_postblend_vd1_h_start_end,

			priv->io_base + _REG(VPP_POSTBLEND_VD1_H_START_END));

		writel_relaxed(priv->viu.vpp_blend_vd2_h_start_end,

			priv->io_base + _REG(VPP_BLEND_VD2_H_START_END));

		writel_relaxed(priv->viu.vpp_postblend_vd1_v_start_end,

			priv->io_base + _REG(VPP_POSTBLEND_VD1_V_START_END));

		writel_relaxed(priv->viu.vpp_blend_vd2_v_start_end,

			priv->io_base + _REG(VPP_BLEND_VD2_V_START_END));

		writel_relaxed(priv->viu.vpp_hsc_region12_startp,

				priv->io_base + _REG(VPP_HSC_REGION12_STARTP));

		writel_relaxed(priv->viu.vpp_hsc_region34_startp,

				priv->io_base + _REG(VPP_HSC_REGION34_STARTP));

		writel_relaxed(priv->viu.vpp_hsc_region4_endp,

				priv->io_base + _REG(VPP_HSC_REGION4_ENDP));

		writel_relaxed(priv->viu.vpp_hsc_start_phase_step,

				priv->io_base + _REG(VPP_HSC_START_PHASE_STEP));

		writel_relaxed(priv->viu.vpp_hsc_region1_phase_slope,

			priv->io_base + _REG(VPP_HSC_REGION1_PHASE_SLOPE));

		writel_relaxed(priv->viu.vpp_hsc_region3_phase_slope,

			priv->io_base + _REG(VPP_HSC_REGION3_PHASE_SLOPE));

		writel_relaxed(priv->viu.vpp_line_in_length,

				priv->io_base + _REG(VPP_LINE_IN_LENGTH));

		writel_relaxed(priv->viu.vpp_preblend_h_size,

				priv->io_base + _REG(VPP_PREBLEND_H_SIZE));

		writel_relaxed(priv->viu.vpp_vsc_region12_startp,

				priv->io_base + _REG(VPP_VSC_REGION12_STARTP));

		writel_relaxed(priv->viu.vpp_vsc_region34_startp,

				priv->io_base + _REG(VPP_VSC_REGION34_STARTP));

		writel_relaxed(priv->viu.vpp_vsc_region4_endp,

				priv->io_base + _REG(VPP_VSC_REGION4_ENDP));

		writel_relaxed(priv->viu.vpp_vsc_start_phase_step,

				priv->io_base + _REG(VPP_VSC_START_PHASE_STEP));

		writel_relaxed(priv->viu.vpp_vsc_ini_phase,

				priv->io_base + _REG(VPP_VSC_INI_PHASE));

		writel_relaxed(priv->viu.vpp_vsc_phase_ctrl,

				priv->io_base + _REG(VPP_VSC_PHASE_CTRL));

		writel_relaxed(priv->viu.vpp_hsc_phase_ctrl,

				priv->io_base + _REG(VPP_HSC_PHASE_CTRL));

		writel_relaxed(0x42, priv->io_base + _REG(VPP_SCALE_COEF_IDX));



		/* Enable VD1 */

		writel_bits_relaxed(VPP_VD1_PREBLEND | VPP_VD1_POSTBLEND |

				    VPP_COLOR_MNG_ENABLE,

				    VPP_VD1_PREBLEND | VPP_VD1_POSTBLEND |

				    VPP_COLOR_MNG_ENABLE,

				    priv->io_base + _REG(VPP_MISC));



		priv->viu.vd1_commit = false;

	}



	drm_crtc_handle_vblank(priv->crtc);



	spin_lock_irqsave(&priv->drm->event_lock, flags);

drivers/gpu/drm/meson/meson_drv.c

+28 −1
Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ 


#include "meson_drv.h"

#include "meson_plane.h"

#include "meson_overlay.h"

#include "meson_crtc.h"

#include "meson_venc_cvbs.h"
@@ -213,6 +214,24 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) 
		ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_osd1);

		if (ret)

			goto free_drm;

		ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_0);

		if (ret) {

			meson_canvas_free(priv->canvas, priv->canvas_id_osd1);

			goto free_drm;

		}

		ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_1);

		if (ret) {

			meson_canvas_free(priv->canvas, priv->canvas_id_osd1);

			meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);

			goto free_drm;

		}

		ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_2);

		if (ret) {

			meson_canvas_free(priv->canvas, priv->canvas_id_osd1);

			meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);

			meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1);

			goto free_drm;

		}

	} else {

		priv->canvas = NULL;
@@ -273,6 +292,10 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) 
	if (ret)

		goto free_drm;



	ret = meson_overlay_create(priv);

	if (ret)

		goto free_drm;



	ret = meson_crtc_create(priv);

	if (ret)

		goto free_drm;
@@ -311,8 +334,12 @@ static void meson_drv_unbind(struct device *dev) 
	struct drm_device *drm = dev_get_drvdata(dev);

	struct meson_drm *priv = drm->dev_private;



	if (priv->canvas)

	if (priv->canvas) {

		meson_canvas_free(priv->canvas, priv->canvas_id_osd1);

		meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);

		meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1);

		meson_canvas_free(priv->canvas, priv->canvas_id_vd1_2);

	}



	drm_dev_unregister(drm);

	drm_kms_helper_poll_fini(drm);