Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f8e6e1b6 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-misc-fixes-2018-10-18' of git://anongit.freedesktop.org/drm/drm-misc into drm-fixes 



drm-misc-fixes for v4.19:
- Fix use of freed memory in drm_mode_setcrtc.
- Reject pixel format changing requests in fb helper.
- Add 6 bpc quirk for HP Pavilion 15-n233sl
- Fix VSDB yCBCr420 Deep Color mode bit definitions

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/647fe5d0-4ec5-57cc-9f23-a4836b29e278@linux.intel.com
parents 35a7f35a 9068e02f

drivers/gpu/drm/drm_crtc.c

+7 −3
Original line number Diff line number Diff line
@@ -567,9 +567,9 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, 
	struct drm_mode_crtc *crtc_req = data;

	struct drm_crtc *crtc;

	struct drm_plane *plane;

	struct drm_connector **connector_set = NULL, *connector;

	struct drm_framebuffer *fb = NULL;

	struct drm_display_mode *mode = NULL;

	struct drm_connector **connector_set, *connector;

	struct drm_framebuffer *fb;

	struct drm_display_mode *mode;

	struct drm_mode_set set;

	uint32_t __user *set_connectors_ptr;

	struct drm_modeset_acquire_ctx ctx;
@@ -598,6 +598,10 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, 
	mutex_lock(&crtc->dev->mode_config.mutex);

	drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);

retry:

	connector_set = NULL;

	fb = NULL;

	mode = NULL;



	ret = drm_modeset_lock_all_ctx(crtc->dev, &ctx);

	if (ret)

		goto out;

drivers/gpu/drm/drm_edid.c

+4 −1
Original line number Diff line number Diff line
@@ -113,6 +113,9 @@ static const struct edid_quirk { 
	/* AEO model 0 reports 8 bpc, but is a 6 bpc panel */

	{ "AEO", 0, EDID_QUIRK_FORCE_6BPC },



	/* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */

	{ "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC },



	/* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */

	{ "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
@@ -4279,7 +4282,7 @@ static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 
	struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;



	dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;

	hdmi->y420_dc_modes |= dc_mask;

	hdmi->y420_dc_modes = dc_mask;

}



static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,

drivers/gpu/drm/drm_fb_helper.c

+26 −65
Original line number Diff line number Diff line
@@ -1580,6 +1580,25 @@ int drm_fb_helper_ioctl(struct fb_info *info, unsigned int cmd, 
}

EXPORT_SYMBOL(drm_fb_helper_ioctl);



static bool drm_fb_pixel_format_equal(const struct fb_var_screeninfo *var_1,

				      const struct fb_var_screeninfo *var_2)

{

	return var_1->bits_per_pixel == var_2->bits_per_pixel &&

	       var_1->grayscale == var_2->grayscale &&

	       var_1->red.offset == var_2->red.offset &&

	       var_1->red.length == var_2->red.length &&

	       var_1->red.msb_right == var_2->red.msb_right &&

	       var_1->green.offset == var_2->green.offset &&

	       var_1->green.length == var_2->green.length &&

	       var_1->green.msb_right == var_2->green.msb_right &&

	       var_1->blue.offset == var_2->blue.offset &&

	       var_1->blue.length == var_2->blue.length &&

	       var_1->blue.msb_right == var_2->blue.msb_right &&

	       var_1->transp.offset == var_2->transp.offset &&

	       var_1->transp.length == var_2->transp.length &&

	       var_1->transp.msb_right == var_2->transp.msb_right;

}



/**

 * drm_fb_helper_check_var - implementation for &fb_ops.fb_check_var

 * @var: screeninfo to check
@@ -1590,7 +1609,6 @@ int drm_fb_helper_check_var(struct fb_var_screeninfo *var, 
{

	struct drm_fb_helper *fb_helper = info->par;

	struct drm_framebuffer *fb = fb_helper->fb;

	int depth;



	if (var->pixclock != 0 || in_dbg_master())

		return -EINVAL;
@@ -1610,72 +1628,15 @@ int drm_fb_helper_check_var(struct fb_var_screeninfo *var, 
		return -EINVAL;

	}



	switch (var->bits_per_pixel) {

	case 16:

		depth = (var->green.length == 6) ? 16 : 15;

		break;

	case 32:

		depth = (var->transp.length > 0) ? 32 : 24;

		break;

	default:

		depth = var->bits_per_pixel;

		break;

	}



	switch (depth) {

	case 8:

		var->red.offset = 0;

		var->green.offset = 0;

		var->blue.offset = 0;

		var->red.length = 8;

		var->green.length = 8;

		var->blue.length = 8;

		var->transp.length = 0;

		var->transp.offset = 0;

		break;

	case 15:

		var->red.offset = 10;

		var->green.offset = 5;

		var->blue.offset = 0;

		var->red.length = 5;

		var->green.length = 5;

		var->blue.length = 5;

		var->transp.length = 1;

		var->transp.offset = 15;

		break;

	case 16:

		var->red.offset = 11;

		var->green.offset = 5;

		var->blue.offset = 0;

		var->red.length = 5;

		var->green.length = 6;

		var->blue.length = 5;

		var->transp.length = 0;

		var->transp.offset = 0;

		break;

	case 24:

		var->red.offset = 16;

		var->green.offset = 8;

		var->blue.offset = 0;

		var->red.length = 8;

		var->green.length = 8;

		var->blue.length = 8;

		var->transp.length = 0;

		var->transp.offset = 0;

		break;

	case 32:

		var->red.offset = 16;

		var->green.offset = 8;

		var->blue.offset = 0;

		var->red.length = 8;

		var->green.length = 8;

		var->blue.length = 8;

		var->transp.length = 8;

		var->transp.offset = 24;

		break;

	default:

	/*

	 * drm fbdev emulation doesn't support changing the pixel format at all,

	 * so reject all pixel format changing requests.

	 */

	if (!drm_fb_pixel_format_equal(var, &info->var)) {

		DRM_DEBUG("fbdev emulation doesn't support changing the pixel format\n");

		return -EINVAL;

	}



	return 0;

}

EXPORT_SYMBOL(drm_fb_helper_check_var);

include/drm/drm_edid.h

+3 −3
Original line number Diff line number Diff line
@@ -214,9 +214,9 @@ struct detailed_timing { 
#define DRM_EDID_HDMI_DC_Y444             (1 << 3)



/* YCBCR 420 deep color modes */

#define DRM_EDID_YCBCR420_DC_48		  (1 << 6)

#define DRM_EDID_YCBCR420_DC_36		  (1 << 5)

#define DRM_EDID_YCBCR420_DC_30		  (1 << 4)

#define DRM_EDID_YCBCR420_DC_48		  (1 << 2)

#define DRM_EDID_YCBCR420_DC_36		  (1 << 1)

#define DRM_EDID_YCBCR420_DC_30		  (1 << 0)

#define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 | \

				    DRM_EDID_YCBCR420_DC_36 | \

				    DRM_EDID_YCBCR420_DC_30)