Loading drivers/soc/qcom/dcc_v2.c +19 −1 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. */ #include <linux/module.h> Loading Loading @@ -87,6 +87,8 @@ #define DCC_MAX_LINK_LIST 8 #define DCC_INVALID_LINK_LIST 0xFF #define DEFAULT_TRANSACTION_TIMEOUT 0x3F enum dcc_func_type { DCC_FUNC_TYPE_CAPTURE, DCC_FUNC_TYPE_CRC, Loading Loading @@ -624,6 +626,9 @@ static int dcc_enable(struct dcc_drvdata *drvdata) int ret = 0; int list; uint32_t ram_cfg_base; uint32_t hw_info; uint32_t transaction_timeout; struct device_node *node = drvdata->dev->of_node; mutex_lock(&drvdata->mutex); Loading Loading @@ -655,6 +660,19 @@ static int dcc_enable(struct dcc_drvdata *drvdata) drvdata->ram_offset/4, DCC_FD_BASE(list)); dcc_writel(drvdata, 0xFFF, DCC_LL_TIMEOUT(list)); hw_info = dcc_readl(drvdata, DCC_HW_INFO); if (hw_info & 0x80) { ret = of_property_read_u32(node, "qcom,transaction_timeout", &transaction_timeout); if (ret) transaction_timeout = DEFAULT_TRANSACTION_TIMEOUT; if (transaction_timeout) dcc_writel(drvdata, transaction_timeout, DCC_TRANS_TIMEOUT(list)); } /* 4. Clears interrupt status register */ dcc_writel(drvdata, 0, DCC_LL_INT_ENABLE(list)); dcc_writel(drvdata, (BIT(0) | BIT(1) | BIT(2)), Loading Loading
drivers/soc/qcom/dcc_v2.c +19 −1 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. */ #include <linux/module.h> Loading Loading @@ -87,6 +87,8 @@ #define DCC_MAX_LINK_LIST 8 #define DCC_INVALID_LINK_LIST 0xFF #define DEFAULT_TRANSACTION_TIMEOUT 0x3F enum dcc_func_type { DCC_FUNC_TYPE_CAPTURE, DCC_FUNC_TYPE_CRC, Loading Loading @@ -624,6 +626,9 @@ static int dcc_enable(struct dcc_drvdata *drvdata) int ret = 0; int list; uint32_t ram_cfg_base; uint32_t hw_info; uint32_t transaction_timeout; struct device_node *node = drvdata->dev->of_node; mutex_lock(&drvdata->mutex); Loading Loading @@ -655,6 +660,19 @@ static int dcc_enable(struct dcc_drvdata *drvdata) drvdata->ram_offset/4, DCC_FD_BASE(list)); dcc_writel(drvdata, 0xFFF, DCC_LL_TIMEOUT(list)); hw_info = dcc_readl(drvdata, DCC_HW_INFO); if (hw_info & 0x80) { ret = of_property_read_u32(node, "qcom,transaction_timeout", &transaction_timeout); if (ret) transaction_timeout = DEFAULT_TRANSACTION_TIMEOUT; if (transaction_timeout) dcc_writel(drvdata, transaction_timeout, DCC_TRANS_TIMEOUT(list)); } /* 4. Clears interrupt status register */ dcc_writel(drvdata, 0, DCC_LL_INT_ENABLE(list)); dcc_writel(drvdata, (BIT(0) | BIT(1) | BIT(2)), Loading