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Commit f8be8e56 authored by Yazen Ghannam's avatar Yazen Ghannam Committed by Borislav Petkov
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EDAC/amd64: Recognize DRAM device type ECC capability 



AMD Family 17h systems support x4 and x16 DRAM devices. However, the
device type is not checked when setting mci.edac_ctl_cap.

Set the appropriate capability flag based on the device type.

Default to x8 DRAM device when neither the x4 or x16 bits are set.

 [ bp: reverse cpk_en check to save an indentation level. ]

Fixes: 2d09d8f3 ("EDAC, amd64: Determine EDAC MC capabilities on Fam17h")
Signed-off-by: default avatarYazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Cc: "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Tony Luck <tony.luck@intel.com>
Link: https://lkml.kernel.org/r/20190821235938.118710-3-Yazen.Ghannam@amd.com
parent d971e28e

drivers/edac/amd64_edac.c

+12 −2
Original line number Diff line number Diff line
@@ -3150,12 +3150,15 @@ static bool ecc_enabled(struct pci_dev *F3, u16 nid) 
static inline void

f17h_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt)

{

	u8 i, ecc_en = 1, cpk_en = 1;

	u8 i, ecc_en = 1, cpk_en = 1, dev_x4 = 1, dev_x16 = 1;



	for_each_umc(i) {

		if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) {

			ecc_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_ENABLED);

			cpk_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_CHIPKILL_CAP);



			dev_x4  &= !!(pvt->umc[i].dimm_cfg & BIT(6));

			dev_x16 &= !!(pvt->umc[i].dimm_cfg & BIT(7));

		}

	}
@@ -3163,8 +3166,15 @@ f17h_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt) 
	if (ecc_en) {

		mci->edac_ctl_cap |= EDAC_FLAG_SECDED;



		if (cpk_en)

		if (!cpk_en)

			return;



		if (dev_x4)

			mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED;

		else if (dev_x16)

			mci->edac_ctl_cap |= EDAC_FLAG_S16ECD16ED;

		else

			mci->edac_ctl_cap |= EDAC_FLAG_S8ECD8ED;

	}

}