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Commit f86748e9 authored by Thomas Gleixner's avatar Thomas Gleixner Committed by Ingo Molnar
Browse files

perf_counter, x86: Implement generalized cache event types, add AMD support 



Fill in amd_hw_cache_event_id[] with the AMD CPU specific events,
for family 0x0f, 0x10 and 0x11.

There's apparently no distinction between load and store events, so
we only fill in the load events.

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <new-submission>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 1123e3ad

arch/x86/kernel/cpu/perf_counter.c

+102 −0
Original line number Original line Diff line number Diff line
@@ -389,6 +389,97 @@ static u64 intel_pmu_raw_event(u64 event) 
	return event & CORE_EVNTSEL_MASK;

	return event & CORE_EVNTSEL_MASK;

}

}





static const u64 amd_0f_hw_cache_event_ids

				[PERF_COUNT_HW_CACHE_MAX]

				[PERF_COUNT_HW_CACHE_OP_MAX]

				[PERF_COUNT_HW_CACHE_RESULT_MAX] =

{

 [ C(L1D) ] = {

	[ C(OP_READ) ] = {

		[ C(RESULT_ACCESS) ] = 0,

		[ C(RESULT_MISS)   ] = 0,

	},

	[ C(OP_WRITE) ] = {

		[ C(RESULT_ACCESS) ] = 0,

		[ C(RESULT_MISS)   ] = 0,

	},

	[ C(OP_PREFETCH) ] = {

		[ C(RESULT_ACCESS) ] = 0,

		[ C(RESULT_MISS)   ] = 0,

	},

 },

 [ C(L1I ) ] = {

	[ C(OP_READ) ] = {

		[ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches  */

		[ C(RESULT_MISS)   ] = 0x0081, /* Instruction cache misses   */

	},

	[ C(OP_WRITE) ] = {

		[ C(RESULT_ACCESS) ] = -1,

		[ C(RESULT_MISS)   ] = -1,

	},

	[ C(OP_PREFETCH) ] = {

		[ C(RESULT_ACCESS) ] = 0,

		[ C(RESULT_MISS)   ] = 0,

	},

 },

 [ C(L2  ) ] = {

	[ C(OP_READ) ] = {

		[ C(RESULT_ACCESS) ] = 0,

		[ C(RESULT_MISS)   ] = 0,

	},

	[ C(OP_WRITE) ] = {

		[ C(RESULT_ACCESS) ] = 0,

		[ C(RESULT_MISS)   ] = 0,

	},

	[ C(OP_PREFETCH) ] = {

		[ C(RESULT_ACCESS) ] = 0,

		[ C(RESULT_MISS)   ] = 0,

	},

 },

 [ C(DTLB) ] = {

	[ C(OP_READ) ] = {

		[ C(RESULT_ACCESS) ] = 0,

		[ C(RESULT_MISS)   ] = 0,

	},

	[ C(OP_WRITE) ] = {

		[ C(RESULT_ACCESS) ] = 0,

		[ C(RESULT_MISS)   ] = 0,

	},

	[ C(OP_PREFETCH) ] = {

		[ C(RESULT_ACCESS) ] = 0,

		[ C(RESULT_MISS)   ] = 0,

	},

 },

 [ C(ITLB) ] = {

	[ C(OP_READ) ] = {

		[ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes        */

		[ C(RESULT_MISS)   ] = 0x0085, /* Instr. fetch ITLB misses   */

	},

	[ C(OP_WRITE) ] = {

		[ C(RESULT_ACCESS) ] = -1,

		[ C(RESULT_MISS)   ] = -1,

	},

	[ C(OP_PREFETCH) ] = {

		[ C(RESULT_ACCESS) ] = -1,

		[ C(RESULT_MISS)   ] = -1,

	},

 },

 [ C(BPU ) ] = {

	[ C(OP_READ) ] = {

		[ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr.      */

		[ C(RESULT_MISS)   ] = 0x00c3, /* Retired Mispredicted BI    */

	},

	[ C(OP_WRITE) ] = {

		[ C(RESULT_ACCESS) ] = -1,

		[ C(RESULT_MISS)   ] = -1,

	},

	[ C(OP_PREFETCH) ] = {

		[ C(RESULT_ACCESS) ] = -1,

		[ C(RESULT_MISS)   ] = -1,

	},

 },

};



/*

/*

 * AMD Performance Monitor K7 and later.

 * AMD Performance Monitor K7 and later.

 */

 */
@@ -1345,6 +1436,17 @@ static int intel_pmu_init(void) 
static int amd_pmu_init(void)

static int amd_pmu_init(void)

{

{

	x86_pmu = amd_pmu;

	x86_pmu = amd_pmu;



	switch (boot_cpu_data.x86) {

	case 0x0f:

	case 0x10:

	case 0x11:

		memcpy(hw_cache_event_ids, amd_0f_hw_cache_event_ids,

		       sizeof(hw_cache_event_ids));



		pr_cont("AMD Family 0f/10/11 events, ");

		break;

	}

	return 0;

	return 0;

}

}