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Commit f83ed203 authored by Dinh Nguyen's avatar Dinh Nguyen Committed by Greg Kroah-Hartman
Browse files

ARM: socfpga: dts: fix qspi node compatible 



[ Upstream commit cb25b11943cbcc5a34531129952870420f8be858 ]

The QSPI flash node needs to have the required "jedec,spi-nor" in the
compatible string.

Fixes: 1df99da8 ("ARM: dts: socfpga: Enable QSPI in Arria10 devkit")
Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 46b9e29d

arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts

+1 −1
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ 
	flash0: n25q00@0 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "n25q00aa";

		compatible = "micron,mt25qu02g", "jedec,spi-nor";

		reg = <0>;

		spi-max-frequency = <100000000>;

arch/arm/boot/dts/socfpga_arria5_socdk.dts

+1 −1
Original line number Diff line number Diff line
@@ -119,7 +119,7 @@ 
	flash: flash@0 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "n25q256a";

		compatible = "micron,n25q256a", "jedec,spi-nor";

		reg = <0>;

		spi-max-frequency = <100000000>;

arch/arm/boot/dts/socfpga_cyclone5_socdk.dts

+1 −1
Original line number Diff line number Diff line
@@ -124,7 +124,7 @@ 
	flash0: n25q00@0 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "n25q00";

		compatible = "micron,mt25qu02g", "jedec,spi-nor";

		reg = <0>;	/* chip select */

		spi-max-frequency = <100000000>;

arch/arm/boot/dts/socfpga_cyclone5_sockit.dts

+1 −1
Original line number Diff line number Diff line
@@ -169,7 +169,7 @@ 
	flash: flash@0 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "n25q00";

		compatible = "micron,mt25qu02g", "jedec,spi-nor";

		reg = <0>;

		spi-max-frequency = <100000000>;

arch/arm/boot/dts/socfpga_cyclone5_socrates.dts

+1 −1
Original line number Diff line number Diff line
@@ -80,7 +80,7 @@ 
	flash: flash@0 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "n25q256a";

		compatible = "micron,n25q256a", "jedec,spi-nor";

		reg = <0>;

		spi-max-frequency = <100000000>;

		m25p,fast-read;