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Commit f806f772 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'BCM54612E' 



Xo Wang says:

====================
Broadcom BCM54612E support

This series is based on tip of torvalds/master.

The first patch adds register definitions from Broadcom docs.

The second patch adds the BCM54612E PHY ID, flags, and device-specific
RGMII internal delay initialization.

I tested on a custom board with an Aspeed AST2500 SOC with its second
MAC connected to this PHY.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 73e42ff7 d92ead16

drivers/net/phy/broadcom.c

+48 −0
Original line number Original line Diff line number Diff line
@@ -337,6 +337,41 @@ static int bcm5481_config_aneg(struct phy_device *phydev) 
	return ret;

	return ret;

}

}





static int bcm54612e_config_aneg(struct phy_device *phydev)

{

	int ret;



	/* First, auto-negotiate. */

	ret = genphy_config_aneg(phydev);



	/* Clear TX internal delay unless requested. */

	if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&

	    (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {

		/* Disable TXD to GTXCLK clock delay (default set) */

		/* Bit 9 is the only field in shadow register 00011 */

		bcm_phy_write_shadow(phydev, 0x03, 0);

	}



	/* Clear RX internal delay unless requested. */

	if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&

	    (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {

		u16 reg;



		/* Errata: reads require filling in the write selector field */

		bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,

				     MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC);

		reg = phy_read(phydev, MII_BCM54XX_AUX_CTL);

		/* Disable RXD to RXC delay (default set) */

		reg &= ~MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW;

		/* Clear shadow selector field */

		reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;

		bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,

				     MII_BCM54XX_AUXCTL_MISC_WREN | reg);

	}



	return ret;

}



static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)

static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)

{

{

	int val;

	int val;
@@ -484,6 +519,18 @@ static struct phy_driver broadcom_drivers[] = { 
	.read_status	= genphy_read_status,

	.read_status	= genphy_read_status,

	.ack_interrupt	= bcm_phy_ack_intr,

	.ack_interrupt	= bcm_phy_ack_intr,

	.config_intr	= bcm_phy_config_intr,

	.config_intr	= bcm_phy_config_intr,

}, {

	.phy_id		= PHY_ID_BCM54612E,

	.phy_id_mask	= 0xfffffff0,

	.name		= "Broadcom BCM54612E",

	.features	= PHY_GBIT_FEATURES |

			  SUPPORTED_Pause | SUPPORTED_Asym_Pause,

	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,

	.config_init	= bcm54xx_config_init,

	.config_aneg	= bcm54612e_config_aneg,

	.read_status	= genphy_read_status,

	.ack_interrupt	= bcm_phy_ack_intr,

	.config_intr	= bcm_phy_config_intr,

}, {

}, {

	.phy_id		= PHY_ID_BCM54616S,

	.phy_id		= PHY_ID_BCM54616S,

	.phy_id_mask	= 0xfffffff0,

	.phy_id_mask	= 0xfffffff0,
@@ -600,6 +647,7 @@ static struct mdio_device_id __maybe_unused broadcom_tbl[] = { 
	{ PHY_ID_BCM5411, 0xfffffff0 },

	{ PHY_ID_BCM5411, 0xfffffff0 },

	{ PHY_ID_BCM5421, 0xfffffff0 },

	{ PHY_ID_BCM5421, 0xfffffff0 },

	{ PHY_ID_BCM5461, 0xfffffff0 },

	{ PHY_ID_BCM5461, 0xfffffff0 },

	{ PHY_ID_BCM54612E, 0xfffffff0 },

	{ PHY_ID_BCM54616S, 0xfffffff0 },

	{ PHY_ID_BCM54616S, 0xfffffff0 },

	{ PHY_ID_BCM5464, 0xfffffff0 },

	{ PHY_ID_BCM5464, 0xfffffff0 },

	{ PHY_ID_BCM5481, 0xfffffff0 },

	{ PHY_ID_BCM5481, 0xfffffff0 },

include/linux/brcmphy.h

+3 −1
Original line number Original line Diff line number Diff line
@@ -18,6 +18,7 @@ 
#define PHY_ID_BCM5421			0x002060e0

#define PHY_ID_BCM5421			0x002060e0

#define PHY_ID_BCM5464			0x002060b0

#define PHY_ID_BCM5464			0x002060b0

#define PHY_ID_BCM5461			0x002060c0

#define PHY_ID_BCM5461			0x002060c0

#define PHY_ID_BCM54612E		0x03625e60

#define PHY_ID_BCM54616S		0x03625d10

#define PHY_ID_BCM54616S		0x03625d10

#define PHY_ID_BCM57780			0x03625d90

#define PHY_ID_BCM57780			0x03625d90
@@ -105,11 +106,12 @@ 
#define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA	0x0800

#define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA	0x0800





#define MII_BCM54XX_AUXCTL_MISC_WREN	0x8000

#define MII_BCM54XX_AUXCTL_MISC_WREN	0x8000

#define MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW	0x0100

#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX	0x0200

#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX	0x0200

#define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC	0x7000

#define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC	0x7000

#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC	0x0007

#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC	0x0007





#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL	0x0000

#define MII_BCM54XX_AUXCTL_SHDWSEL_MASK	0x0007





/*

/*

 * Broadcom LED source encodings.  These are used in BCM5461, BCM5481,

 * Broadcom LED source encodings.  These are used in BCM5461, BCM5481,