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Commit f7b2ed43 authored by Rafael J. Wysocki's avatar Rafael J. Wysocki
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Merge branch 'cpufreq-fixes' of git://git.linaro.org/people/vireshk/linux into pm-cpufreq

Pull cpufreq fixes for v3.12 from Viresh Kumar.

* 'cpufreq-fixes' of git://git.linaro.org/people/vireshk/linux:
  cpufreq: imx6q: Fix clock enable balance
  cpufreq: tegra: fix the wrong clock name
parents 09198f8f fae19b84
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+0 −17
Original line number Diff line number Diff line
@@ -117,28 +117,11 @@ static int imx6q_set_target(struct cpufreq_policy *policy,
	 *  - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
	 *  - Disable pll2_pfd2_396m_clk
	 */
	clk_prepare_enable(pll2_pfd2_396m_clk);
	clk_set_parent(step_clk, pll2_pfd2_396m_clk);
	clk_set_parent(pll1_sw_clk, step_clk);
	if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
		clk_set_rate(pll1_sys_clk, freqs.new * 1000);
		/*
		 * If we are leaving 396 MHz set-point, we need to enable
		 * pll1_sys_clk and disable pll2_pfd2_396m_clk to keep
		 * their use count correct.
		 */
		if (freqs.old * 1000 <= clk_get_rate(pll2_pfd2_396m_clk)) {
			clk_prepare_enable(pll1_sys_clk);
			clk_disable_unprepare(pll2_pfd2_396m_clk);
		}
		clk_set_parent(pll1_sw_clk, pll1_sys_clk);
		clk_disable_unprepare(pll2_pfd2_396m_clk);
	} else {
		/*
		 * Disable pll1_sys_clk if pll2_pfd2_396m_clk is sufficient
		 * to provide the frequency.
		 */
		clk_disable_unprepare(pll1_sys_clk);
	}

	/* Ensure the arm clock divider is what we expect */
+2 −2
Original line number Diff line number Diff line
@@ -255,7 +255,7 @@ static struct cpufreq_driver tegra_cpufreq_driver = {

static int __init tegra_cpufreq_init(void)
{
	cpu_clk = clk_get_sys(NULL, "cpu");
	cpu_clk = clk_get_sys(NULL, "cclk");
	if (IS_ERR(cpu_clk))
		return PTR_ERR(cpu_clk);

@@ -263,7 +263,7 @@ static int __init tegra_cpufreq_init(void)
	if (IS_ERR(pll_x_clk))
		return PTR_ERR(pll_x_clk);

	pll_p_clk = clk_get_sys(NULL, "pll_p_cclk");
	pll_p_clk = clk_get_sys(NULL, "pll_p");
	if (IS_ERR(pll_p_clk))
		return PTR_ERR(pll_p_clk);