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Commit f78c3422 authored by Tom St Denis's avatar Tom St Denis Committed by Alex Deucher
Browse files

drm/amdgpu/uvd6: De-numberify startup 



To make the code more legible various numerical constants
have been changed to their #define'ed MASKs.

Signed-off-by: default avatarTom St Denis <tom.stdenis@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 21718497

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

+25 −14
Original line number Diff line number Diff line
@@ -386,7 +386,7 @@ static int uvd_v6_0_start(struct amdgpu_device *adev) 
	int i, j, r;



	/* disable DPG */

	WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2));

	WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);



	/* disable byte swapping */

	lmi_swap_cntl = 0;
@@ -405,17 +405,21 @@ static int uvd_v6_0_start(struct amdgpu_device *adev) 
	}



	/* disable interupt */

	WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));

	WREG32_P(mmUVD_MASTINT_EN, 0, ~UVD_MASTINT_EN__VCPU_EN_MASK);



	/* stall UMC and register bus before resetting VCPU */

	WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));

	WREG32_P(mmUVD_LMI_CTRL2, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);

	mdelay(1);



	/* put LMI, VCPU, RBC etc... into reset */

	WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |

		UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |

		UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |

		UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |

	WREG32(mmUVD_SOFT_RESET,

		UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |

		UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |

		UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |

		UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |

		UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |

		UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |

		UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |

		UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);

	mdelay(5);
@@ -424,8 +428,13 @@ static int uvd_v6_0_start(struct amdgpu_device *adev) 
	mdelay(5);



	/* initialize UVD memory controller */

	WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |

			     (1 << 21) | (1 << 9) | (1 << 20));

	WREG32(mmUVD_LMI_CTRL,

		(0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |

		UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |

		UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |

		UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |

		UVD_LMI_CTRL__REQ_MODE_MASK |

		UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK);



#ifdef __BIG_ENDIAN

	/* swap (8 in 32) RB and IB */
@@ -447,10 +456,10 @@ static int uvd_v6_0_start(struct amdgpu_device *adev) 
	mdelay(5);



	/* enable VCPU clock */

	WREG32(mmUVD_VCPU_CNTL,  1 << 9);

	WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);



	/* enable UMC */

	WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));

	WREG32_P(mmUVD_LMI_CTRL2, 0, ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);



	/* boot up the VCPU */

	WREG32(mmUVD_SOFT_RESET, 0);
@@ -484,10 +493,12 @@ static int uvd_v6_0_start(struct amdgpu_device *adev) 
		return r;

	}

	/* enable master interrupt */

	WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1));

	WREG32_P(mmUVD_MASTINT_EN,

		(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),

		~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));



	/* clear the bit 4 of UVD_STATUS */

	WREG32_P(mmUVD_STATUS, 0, ~(2 << 1));

	WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));



	rb_bufsz = order_base_2(ring->ring_size);

	tmp = 0;