Commit f77084d9 authored Oct 17, 2018 by Sebastian Andrzej Siewior Committed by Thomas Gleixner Oct 29, 2018

x86/mm/pat: Disable preemption around __flush_tlb_all()



The WARN_ON_ONCE(__read_cr3() != build_cr3()) in switch_mm_irqs_off()
triggers every once in a while during a snapshotted system upgrade.

The warning triggers since commit decab088 ("x86/mm: Remove
preempt_disable/enable() from __native_flush_tlb()"). The callchain is:

  get_page_from_freelist() -> post_alloc_hook() -> __kernel_map_pages()

with CONFIG_DEBUG_PAGEALLOC enabled.

Disable preemption during CR3 reset / __flush_tlb_all() and add a comment
why preemption has to be disabled so it won't be removed accidentaly.

Add another preemptible() check in __flush_tlb_all() to catch callers with
enabled preemption when PGE is enabled, because PGE enabled does not
trigger the warning in __native_flush_tlb(). Suggested by Andy Lutomirski.

Fixes: decab088 ("x86/mm: Remove preempt_disable/enable() from __native_flush_tlb()")
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20181017103432.zgv46nlu3hc7k4rq@linutronix.de

parent 8af19095

arch/x86/include/asm/tlbflush.h

+6 −0

Original line number	Diff line number	Diff line
		@@ -453,6 +453,12 @@ static inline void __native_flush_tlb_one_user(unsigned long addr)
		*/
		static inline void __flush_tlb_all(void)
		{
		/*
		* This is to catch users with enabled preemption and the PGE feature
		* and don't trigger the warning in __native_flush_tlb().
		*/
		VM_WARN_ON_ONCE(preemptible());

		if (boot_cpu_has(X86_FEATURE_PGE)) {
		__flush_tlb_global();
		} else {

arch/x86/mm/pageattr.c

+5 −1

Original line number	Diff line number	Diff line
		@@ -2309,9 +2309,13 @@ void __kernel_map_pages(struct page *page, int numpages, int enable)

		/*
		* We should perform an IPI and flush all tlbs,
		* but that can deadlock->flush only current cpu:
		* but that can deadlock->flush only current cpu.
		* Preemption needs to be disabled around __flush_tlb_all() due to
		* CR3 reload in __native_flush_tlb().
		*/
		preempt_disable();
		__flush_tlb_all();
		preempt_enable();

		arch_flush_lazy_mmu_mode();
		}