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Commit f75dd8bd authored by Andrew-sh Cheng's avatar Andrew-sh Cheng Committed by Matthias Brugger
Browse files

arm64: dts: mediatek: add mt2712 cpufreq related device nodes 



Add opp v2 information,
and also add clocks, regulators and opp information into cpu nodes

Signed-off-by: default avatarAndrew-sh Cheng <andrew-sh.cheng@mediatek.com>
Acked-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 5d483970

arch/arm64/boot/dts/mediatek/mt2712-evb.dts

+27 −0
Original line number Diff line number Diff line
@@ -24,6 +24,33 @@ 
	chosen {

		stdout-path = "serial0:921600n8";

	};



	cpus_fixed_vproc0: fixedregulator@0 {

		compatible = "regulator-fixed";

		regulator-name = "vproc_buck0";

		regulator-min-microvolt = <1000000>;

		regulator-max-microvolt = <1000000>;

	};



	cpus_fixed_vproc1: fixedregulator@1 {

		compatible = "regulator-fixed";

		regulator-name = "vproc_buck1";

		regulator-min-microvolt = <1000000>;

		regulator-max-microvolt = <1000000>;

	};



};



&cpu0 {

	proc-supply = <&cpus_fixed_vproc0>;

};



&cpu1 {

	proc-supply = <&cpus_fixed_vproc0>;

};



&cpu2 {

	proc-supply = <&cpus_fixed_vproc1>;

};



&uart0 {

arch/arm64/boot/dts/mediatek/mt2712e.dtsi

+57 −0
Original line number Diff line number Diff line
@@ -15,6 +15,48 @@ 
	#address-cells = <2>;

	#size-cells = <2>;



	cluster0_opp: opp_table0 {

		compatible = "operating-points-v2";

		opp-shared;

		opp00 {

			opp-hz = /bits/ 64 <598000000>;

			opp-microvolt = <1000000>;

		};

		opp01 {

			opp-hz = /bits/ 64 <702000000>;

			opp-microvolt = <1000000>;

		};

		opp02 {

			opp-hz = /bits/ 64 <793000000>;

			opp-microvolt = <1000000>;

		};

	};



	cluster1_opp: opp_table1 {

		compatible = "operating-points-v2";

		opp-shared;

		opp00 {

			opp-hz = /bits/ 64 <598000000>;

			opp-microvolt = <1000000>;

		};

		opp01 {

			opp-hz = /bits/ 64 <702000000>;

			opp-microvolt = <1000000>;

		};

		opp02 {

			opp-hz = /bits/ 64 <793000000>;

			opp-microvolt = <1000000>;

		};

		opp03 {

			opp-hz = /bits/ 64 <897000000>;

			opp-microvolt = <1000000>;

		};

		opp04 {

			opp-hz = /bits/ 64 <1001000000>;

			opp-microvolt = <1000000>;

		};

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;
@@ -40,6 +82,11 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a35";

			reg = <0x000>;

			clocks = <&mcucfg CLK_MCU_MP0_SEL>,

				<&topckgen CLK_TOP_F_MP0_PLL1>;

			clock-names = "cpu", "intermediate";

			proc-supply = <&cpus_fixed_vproc0>;

			operating-points-v2 = <&cluster0_opp>;

			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;

		};
@@ -48,6 +95,11 @@ 
			compatible = "arm,cortex-a35";

			reg = <0x001>;

			enable-method = "psci";

			clocks = <&mcucfg CLK_MCU_MP0_SEL>,

				<&topckgen CLK_TOP_F_MP0_PLL1>;

			clock-names = "cpu", "intermediate";

			proc-supply = <&cpus_fixed_vproc0>;

			operating-points-v2 = <&cluster0_opp>;

			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;

		};
@@ -56,6 +108,11 @@ 
			compatible = "arm,cortex-a72";

			reg = <0x200>;

			enable-method = "psci";

			clocks = <&mcucfg CLK_MCU_MP2_SEL>,

				<&topckgen CLK_TOP_F_BIG_PLL1>;

			clock-names = "cpu", "intermediate";

			proc-supply = <&cpus_fixed_vproc1>;

			operating-points-v2 = <&cluster1_opp>;

			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;

		};