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Commit f68ba691 authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding
Browse files

drm/tegra: dc: Link DC1 to DC0 on Tegra20 



Hardware reset isn't actually broken on Tegra20, but there is a
dependency on the first display controller to be taken out of reset for
the second to be enabled successfully. Model this dependency using a PM
device link.

Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
[treding@nvidia.com: minor cleanups, extend commit message]
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 39f55c61

drivers/gpu/drm/tegra/dc.c

+64 −30
Original line number Diff line number Diff line
@@ -1882,7 +1882,7 @@ static const struct tegra_dc_soc_info tegra20_dc_soc_info = { 
	.supports_blending = false,

	.pitch_align = 8,

	.has_powergate = false,

	.broken_reset = true,

	.coupled_pm = true,

	.has_nvdisplay = false,

	.num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),

	.primary_formats = tegra20_primary_formats,
@@ -1898,7 +1898,7 @@ static const struct tegra_dc_soc_info tegra30_dc_soc_info = { 
	.supports_blending = false,

	.pitch_align = 8,

	.has_powergate = false,

	.broken_reset = false,

	.coupled_pm = false,

	.has_nvdisplay = false,

	.num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),

	.primary_formats = tegra20_primary_formats,
@@ -1914,7 +1914,7 @@ static const struct tegra_dc_soc_info tegra114_dc_soc_info = { 
	.supports_blending = false,

	.pitch_align = 64,

	.has_powergate = true,

	.broken_reset = false,

	.coupled_pm = false,

	.has_nvdisplay = false,

	.num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),

	.primary_formats = tegra114_primary_formats,
@@ -1930,7 +1930,7 @@ static const struct tegra_dc_soc_info tegra124_dc_soc_info = { 
	.supports_blending = true,

	.pitch_align = 64,

	.has_powergate = true,

	.broken_reset = false,

	.coupled_pm = false,

	.has_nvdisplay = false,

	.num_primary_formats = ARRAY_SIZE(tegra124_primary_formats),

	.primary_formats = tegra114_primary_formats,
@@ -1946,7 +1946,7 @@ static const struct tegra_dc_soc_info tegra210_dc_soc_info = { 
	.supports_blending = true,

	.pitch_align = 64,

	.has_powergate = true,

	.broken_reset = false,

	.coupled_pm = false,

	.has_nvdisplay = false,

	.num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),

	.primary_formats = tegra114_primary_formats,
@@ -1996,7 +1996,7 @@ static const struct tegra_dc_soc_info tegra186_dc_soc_info = { 
	.supports_blending = true,

	.pitch_align = 64,

	.has_powergate = false,

	.broken_reset = false,

	.coupled_pm = false,

	.has_nvdisplay = true,

	.wgrps = tegra186_dc_wgrps,

	.num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps),
@@ -2064,6 +2064,43 @@ static int tegra_dc_parse_dt(struct tegra_dc *dc) 
	return 0;

}



static int tegra_dc_match_by_pipe(struct device *dev, void *data)

{

	struct tegra_dc *dc = dev_get_drvdata(dev);

	unsigned int pipe = (unsigned long)data;



	return dc->pipe == pipe;

}



static int tegra_dc_couple(struct tegra_dc *dc)

{

	/*

	 * On Tegra20, DC1 requires DC0 to be taken out of reset in order to

	 * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND /

	 * POWER_CONTROL registers during CRTC enabling.

	 */

	if (dc->soc->coupled_pm && dc->pipe == 1) {

		u32 flags = DL_FLAG_PM_RUNTIME | DL_FLAG_AUTOREMOVE;

		struct device_link *link;

		struct device *partner;



		partner = driver_find_device(dc->dev->driver, NULL, 0,

					     tegra_dc_match_by_pipe);

		if (!partner)

			return -EPROBE_DEFER;



		link = device_link_add(dc->dev, partner, flags);

		if (!link) {

			dev_err(dc->dev, "failed to link controllers\n");

			return -EINVAL;

		}



		dev_dbg(dc->dev, "coupled to %s\n", dev_name(partner));

	}



	return 0;

}



static int tegra_dc_probe(struct platform_device *pdev)

{

	struct resource *regs;
@@ -2083,6 +2120,10 @@ static int tegra_dc_probe(struct platform_device *pdev) 
	if (err < 0)

		return err;



	err = tegra_dc_couple(dc);

	if (err < 0)

		return err;



	dc->clk = devm_clk_get(&pdev->dev, NULL);

	if (IS_ERR(dc->clk)) {

		dev_err(&pdev->dev, "failed to get clock\n");
@@ -2096,7 +2137,6 @@ static int tegra_dc_probe(struct platform_device *pdev) 
	}



	/* assert reset and disable clock */

	if (!dc->soc->broken_reset) {

	err = clk_prepare_enable(dc->clk);

	if (err < 0)

		return err;
@@ -2110,7 +2150,6 @@ static int tegra_dc_probe(struct platform_device *pdev) 
	usleep_range(2000, 4000);



	clk_disable_unprepare(dc->clk);

	}



	if (dc->soc->has_powergate) {

		if (dc->pipe == 0)
@@ -2184,13 +2223,11 @@ static int tegra_dc_suspend(struct device *dev) 
	struct tegra_dc *dc = dev_get_drvdata(dev);

	int err;



	if (!dc->soc->broken_reset) {

	err = reset_control_assert(dc->rst);

	if (err < 0) {

		dev_err(dev, "failed to assert reset: %d\n", err);

		return err;

	}

	}



	if (dc->soc->has_powergate)

		tegra_powergate_power_off(dc->powergate);
@@ -2219,15 +2256,12 @@ static int tegra_dc_resume(struct device *dev) 
			return err;

		}



		if (!dc->soc->broken_reset) {

		err = reset_control_deassert(dc->rst);

		if (err < 0) {

				dev_err(dev,

					"failed to deassert reset: %d\n", err);

			dev_err(dev, "failed to deassert reset: %d\n", err);

			return err;

		}

	}

	}



	return 0;

}

drivers/gpu/drm/tegra/dc.h

+1 −1
Original line number Diff line number Diff line
@@ -58,7 +58,7 @@ struct tegra_dc_soc_info { 
	bool supports_blending;

	unsigned int pitch_align;

	bool has_powergate;

	bool broken_reset;

	bool coupled_pm;

	bool has_nvdisplay;

	const struct tegra_windowgroup_soc *wgrps;

	unsigned int num_wgrps;