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Commit f68b18fd authored by Marek Szyprowski's avatar Marek Szyprowski Committed by Krzysztof Kozlowski
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arm64: dts: exynos: Update DWC3 modules on Exynos5433 SoCs 



Update DWC3 hardware modules to Exynos5433 specific variant: change
compatible name and add all required clocks (both to the glue node and
DWC3 core node).

Signed-off-by: default avatarMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
parent 65102238

arch/arm64/boot/dts/exynos/exynos5433.dtsi

+18 −6
Original line number Original line Diff line number Diff line
@@ -1559,10 +1559,12 @@ 
		};

		};





		usbdrd30: usbdrd {

		usbdrd30: usbdrd {

			compatible = "samsung,exynos5250-dwusb3";

			compatible = "samsung,exynos5433-dwusb3";

			clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,

			clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,

				<&cmu_fsys CLK_SCLK_USBDRD30>;

				<&cmu_fsys CLK_SCLK_USBDRD30>,

			clock-names = "usbdrd30", "usbdrd30_susp_clk";

				<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,

				<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>;

			clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk";

			#address-cells = <1>;

			#address-cells = <1>;

			#size-cells = <1>;

			#size-cells = <1>;

			ranges;

			ranges;
@@ -1570,6 +1572,10 @@ 




			usbdrd_dwc3: dwc3@15400000 {

			usbdrd_dwc3: dwc3@15400000 {

				compatible = "snps,dwc3";

				compatible = "snps,dwc3";

				clocks = <&cmu_fsys CLK_SCLK_USBDRD30>,

					<&cmu_fsys CLK_ACLK_USBDRD30>,

					<&cmu_fsys CLK_SCLK_USBDRD30>;

				clock-names = "ref", "bus_early", "suspend";

				reg = <0x15400000 0x10000>;

				reg = <0x15400000 0x10000>;

				interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;

				interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;

				phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>;

				phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>;
@@ -1606,10 +1612,12 @@ 
		};

		};





		usbhost30: usbhost {

		usbhost30: usbhost {

			compatible = "samsung,exynos5250-dwusb3";

			compatible = "samsung,exynos5433-dwusb3";

			clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,

			clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,

				<&cmu_fsys CLK_SCLK_USBHOST30>;

				<&cmu_fsys CLK_SCLK_USBHOST30>,

			clock-names = "usbdrd30", "usbdrd30_susp_clk";

				<&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,

				<&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>;

			clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk";

			#address-cells = <1>;

			#address-cells = <1>;

			#size-cells = <1>;

			#size-cells = <1>;

			ranges;

			ranges;
@@ -1617,6 +1625,10 @@ 




			usbhost_dwc3: dwc3@15a00000 {

			usbhost_dwc3: dwc3@15a00000 {

				compatible = "snps,dwc3";

				compatible = "snps,dwc3";

				clocks = <&cmu_fsys CLK_SCLK_USBHOST30>,

					<&cmu_fsys CLK_ACLK_USBHOST30>,

					<&cmu_fsys CLK_SCLK_USBHOST30>;

				clock-names = "ref", "bus_early", "suspend";

				reg = <0x15a00000 0x10000>;

				reg = <0x15a00000 0x10000>;

				interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;

				interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;

				phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>;

				phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>;