Commit f665bd15 authored Aug 30, 2016 by Bharat Kumar Gogada Committed by Bjorn Helgaas Sep 13, 2016

PCI: xilinx-nwl: Enable all MSI interrupts using MSI mask



The current mask enables and allows only one MSI interrupt on each MSI
line.  Enable all MSI interrupts, which will also support Endpoints with
multi-MSI support.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

parent c2a7ff18

drivers/pci/host/pcie-xilinx-nwl.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -120,8 +120,8 @@
		MSGF_LEG_SR_INTC \| MSGF_LEG_SR_INTD)

		/* MSI interrupt status mask bits */
		#define MSGF_MSI_SR_LO_MASK BIT(0)
		#define MSGF_MSI_SR_HI_MASK BIT(0)
		#define MSGF_MSI_SR_LO_MASK GENMASK(31, 0)
		#define MSGF_MSI_SR_HI_MASK GENMASK(31, 0)

		#define MSII_PRESENT BIT(0)
		#define MSII_ENABLE BIT(0)