+16
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Cyclone5 and Arria10 doesn't have the same memory map for UART1. Split the SOCFPGA_UART1 into 2 options to allow debugging on UART1 for Cyclone5. Signed-off-by:Clément Péron <peron.clem@gmail.com> Signed-off-by:
Dinh Nguyen <dinguyen@kernel.org>