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Commit f57f9371 authored by Oscar Mateo's avatar Oscar Mateo Committed by Rodrigo Vivi
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drm/i915/icl: WaAllowUMDToModifySamplerMode 



Required for Bindless samplers.
Userspace consumer: mesa

V2: Rebase
V3: Update commit message

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: default avatarOscar Mateo <oscar.mateo@intel.com>
Signed-off-by: default avatarRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: default avatarAnusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181030084504.21537-4-radhakrishna.sripada@intel.com
parent 6a00b8fe

drivers/gpu/drm/i915/i915_reg.h

+2 −0
Original line number Diff line number Diff line
@@ -8652,6 +8652,8 @@ enum { 
#define GAMW_ECO_DEV_RW_IA_REG			_MMIO(0x4080)

#define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE	(1 << 7)



#define GEN10_SAMPLER_MODE		_MMIO(0xE18C)



/* IVYBRIDGE DPF */

#define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */

#define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff << 14)

drivers/gpu/drm/i915/intel_workarounds.c

+3 −0
Original line number Diff line number Diff line
@@ -1018,6 +1018,9 @@ static void icl_whitelist_build(struct whitelist *w) 
{

	/* WaAllowUMDToModifyHalfSliceChicken7:icl */

	whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);



	/* WaAllowUMDToModifySamplerMode:icl */

	whitelist_reg(w, GEN10_SAMPLER_MODE);

}



static struct whitelist *whitelist_build(struct intel_engine_cs *engine,