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Commit f572a913 authored by Alexandre Torgue's avatar Alexandre Torgue Committed by Greg Kroah-Hartman
Browse files

ARM: dts: stm32: fix timer nodes on STM32 MCU to prevent warnings 



[ Upstream commit 2388f14d8747f8304e26ee870790e188c9431efd ]

Prevent warning seen with "make dtbs_check W=1" command:

Warning (avoid_unnecessary_addr_size): /soc/timers@40001c00: unnecessary
address-cells/size-cells without "ranges" or child "reg" property

Reviewed-by: default avatarFabrice Gasnier <fabrice.gasnier@foss.st.com>
Signed-off-by: default avatarAlexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 95e79547

arch/arm/boot/dts/stm32f429.dtsi

+0 −8
Original line number Diff line number Diff line
@@ -283,8 +283,6 @@ 
		};



		timers13: timers@40001c00 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "st,stm32-timers";

			reg = <0x40001C00 0x400>;

			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
@@ -299,8 +297,6 @@ 
		};



		timers14: timers@40002000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "st,stm32-timers";

			reg = <0x40002000 0x400>;

			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
@@ -623,8 +619,6 @@ 
		};



		timers10: timers@40014400 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "st,stm32-timers";

			reg = <0x40014400 0x400>;

			clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
@@ -639,8 +633,6 @@ 
		};



		timers11: timers@40014800 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "st,stm32-timers";

			reg = <0x40014800 0x400>;

			clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;

arch/arm/boot/dts/stm32f746.dtsi

+0 −8
Original line number Diff line number Diff line
@@ -265,8 +265,6 @@ 
		};



		timers13: timers@40001c00 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "st,stm32-timers";

			reg = <0x40001C00 0x400>;

			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
@@ -281,8 +279,6 @@ 
		};



		timers14: timers@40002000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "st,stm32-timers";

			reg = <0x40002000 0x400>;

			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
@@ -533,8 +529,6 @@ 
		};



		timers10: timers@40014400 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "st,stm32-timers";

			reg = <0x40014400 0x400>;

			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
@@ -549,8 +543,6 @@ 
		};



		timers11: timers@40014800 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "st,stm32-timers";

			reg = <0x40014800 0x400>;

			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;

arch/arm/boot/dts/stm32h743.dtsi

+0 −4
Original line number Diff line number Diff line
@@ -438,8 +438,6 @@ 
		};



		lptimer4: timer@58002c00 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "st,stm32-lptimer";

			reg = <0x58002c00 0x400>;

			clocks = <&rcc LPTIM4_CK>;
@@ -454,8 +452,6 @@ 
		};



		lptimer5: timer@58003000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "st,stm32-lptimer";

			reg = <0x58003000 0x400>;

			clocks = <&rcc LPTIM5_CK>;