Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f5697226 authored by Abel Vesa's avatar Abel Vesa Committed by Shawn Guo
Browse files

clk: imx6q: Do not reparent uninitialized IMX6QDL_CLK_PERIPH2 clock 



The clock is registered later than these two re-parentings.

Signed-off-by: default avatarAbel Vesa <abel.vesa@nxp.com>
Reviewed-by: default avatarStephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent fa757474

drivers/clk/imx/clk-imx6q.c

+0 −8
Original line number Diff line number Diff line
@@ -280,12 +280,6 @@ static void mmdc_ch1_disable(void __iomem *ccm_base) 
	clk_set_parent(clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL],

		       clk[IMX6QDL_CLK_PLL3_USB_OTG]);



	/*

	 * Handshake with mmdc_ch1 module must be masked when changing

	 * periph2_clk_sel.

	 */

	clk_set_parent(clk[IMX6QDL_CLK_PERIPH2], clk[IMX6QDL_CLK_PERIPH2_CLK2]);



	/* Disable pll3_sw_clk by selecting the bypass clock source */

	reg = readl_relaxed(ccm_base + CCM_CCSR);

	reg |= CCSR_PLL3_SW_CLK_SEL;
@@ -300,8 +294,6 @@ static void mmdc_ch1_reenable(void __iomem *ccm_base) 
	reg = readl_relaxed(ccm_base + CCM_CCSR);

	reg &= ~CCSR_PLL3_SW_CLK_SEL;

	writel_relaxed(reg, ccm_base + CCM_CCSR);



	clk_set_parent(clk[IMX6QDL_CLK_PERIPH2], clk[IMX6QDL_CLK_PERIPH2_PRE]);

}



/*