Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f51424f8 authored by Nilaan Gunabalachandran's avatar Nilaan Gunabalachandran
Browse files

disp: msm: sde: ctl hw flush ops clean up 



Using individual flush functions for each active hw blk
is not scable-able for future use. Clean up the ops to merge
all flush functions into one and manage HW block id
with same API.

Change-Id: I62afbc51fa7d345b3a1f5721e5e09661a4215f7a
Signed-off-by: default avatarNilaan Gunabalachandran <ngunabal@codeaurora.org>
parent 664e64b8

msm/sde/sde_encoder.c

+18 −15
Original line number Diff line number Diff line
@@ -2731,9 +2731,10 @@ void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc, 
			wb_enc->hw_wb->ops.bind_pingpong_blk(wb_enc->hw_wb,

					false, phys_enc->hw_pp->idx);



			if (phys_enc->hw_ctl->ops.update_bitmask_wb)

				phys_enc->hw_ctl->ops.update_bitmask_wb(

			if (phys_enc->hw_ctl->ops.update_bitmask)

				phys_enc->hw_ctl->ops.update_bitmask(

						phys_enc->hw_ctl,

						SDE_HW_FLUSH_WB,

						wb_enc->hw_wb->idx, true);

		}

	} else {
@@ -2742,9 +2743,10 @@ void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc, 
					phys_enc->hw_intf, false,

					phys_enc->hw_pp->idx);



			if (phys_enc->hw_ctl->ops.update_bitmask_intf)

				phys_enc->hw_ctl->ops.update_bitmask_intf(

			if (phys_enc->hw_ctl->ops.update_bitmask)

				phys_enc->hw_ctl->ops.update_bitmask(

						phys_enc->hw_ctl,

						SDE_HW_FLUSH_INTF,

						phys_enc->hw_intf->idx, true);

		}

	}
@@ -2752,10 +2754,10 @@ void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc, 
	if (phys_enc->hw_pp && phys_enc->hw_pp->ops.reset_3d_mode) {

		phys_enc->hw_pp->ops.reset_3d_mode(phys_enc->hw_pp);



		if (phys_enc->hw_ctl->ops.update_bitmask_merge3d &&

		if (phys_enc->hw_ctl->ops.update_bitmask &&

				phys_enc->hw_pp->merge_3d)

			phys_enc->hw_ctl->ops.update_bitmask_merge3d(

					phys_enc->hw_ctl,

			phys_enc->hw_ctl->ops.update_bitmask(

					phys_enc->hw_ctl, SDE_HW_FLUSH_MERGE_3D,

					phys_enc->hw_pp->merge_3d->idx, true);

	}
@@ -2764,9 +2766,9 @@ void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc, 
		phys_enc->hw_cdm->ops.bind_pingpong_blk(phys_enc->hw_cdm,

				false, phys_enc->hw_pp->idx);



		if (phys_enc->hw_ctl->ops.update_bitmask_cdm)

			phys_enc->hw_ctl->ops.update_bitmask_cdm(

					phys_enc->hw_ctl,

		if (phys_enc->hw_ctl->ops.update_bitmask)

			phys_enc->hw_ctl->ops.update_bitmask(

					phys_enc->hw_ctl, SDE_HW_FLUSH_CDM,

					phys_enc->hw_cdm->idx, true);

	}
@@ -3112,18 +3114,18 @@ static inline void _sde_encoder_trigger_flush(struct drm_encoder *drm_enc, 
	pend_ret_fence_cnt = atomic_read(&phys->pending_retire_fence_cnt);



	if (phys->hw_intf && phys->hw_intf->cap->type == INTF_DP &&

			ctl->ops.update_bitmask_periph) {

			ctl->ops.update_bitmask) {

		/* perform peripheral flush on every frame update for dp dsc */

		if (phys->comp_type == MSM_DISPLAY_COMPRESSION_DSC &&

				phys->comp_ratio && c_conn->ops.update_pps) {

			c_conn->ops.update_pps(phys->connector, NULL,

					c_conn->display);

			ctl->ops.update_bitmask_periph(ctl,

			ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_PERIPH,

					phys->hw_intf->idx, 1);

		}



		if (sde_enc->dynamic_hdr_updated)

			ctl->ops.update_bitmask_periph(ctl,

			ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_PERIPH,

					phys->hw_intf->idx, 1);

	}
@@ -3816,9 +3818,10 @@ static int _helper_flush_qsync(struct sde_encoder_phys *phys_enc) 
			if (!hw_intf)

				continue;



			if (phys_enc->hw_ctl->ops.update_bitmask_intf)

				phys_enc->hw_ctl->ops.update_bitmask_intf(

			if (phys_enc->hw_ctl->ops.update_bitmask)

				phys_enc->hw_ctl->ops.update_bitmask(

						phys_enc->hw_ctl,

						SDE_HW_FLUSH_INTF,

						hw_intf->idx, 1);



			intf_valid = true;

msm/sde/sde_encoder_dce.c

+18 −14
Original line number Diff line number Diff line
@@ -465,8 +465,9 @@ static int _dce_dsc_setup(struct sde_encoder_virt *sde_enc, 
					&cfg,

					active);



		if (hw_ctl->ops.update_bitmask_dsc)

			hw_ctl->ops.update_bitmask_dsc(hw_ctl,

		if (hw_ctl->ops.update_bitmask)

			hw_ctl->ops.update_bitmask(hw_ctl,

					SDE_HW_FLUSH_DSC,

					hw_dsc[i]->idx, active);



		SDE_DEBUG_DCE(sde_enc,
@@ -486,9 +487,9 @@ static int _dce_dsc_setup(struct sde_encoder_virt *sde_enc, 
						&cfg,

						!disable_merge_3d);



			if (hw_ctl->ops.update_bitmask_merge3d)

				hw_ctl->ops.update_bitmask_merge3d(

						hw_ctl,

			if (hw_ctl->ops.update_bitmask)

				hw_ctl->ops.update_bitmask(

						hw_ctl, SDE_HW_FLUSH_MERGE_3D,

						hw_pp[i]->merge_3d->idx, true);



			SDE_DEBUG("mode_3d %s, on CTL_%d PP-%d merge3d:%d\n",
@@ -635,8 +636,9 @@ static int _dce_vdc_setup(struct sde_encoder_virt *sde_enc, 
					&cfg,

					active);



		if (hw_ctl->ops.update_bitmask_vdc)

			hw_ctl->ops.update_bitmask_vdc(hw_ctl,

		if (hw_ctl->ops.update_bitmask)

			hw_ctl->ops.update_bitmask(hw_ctl,

					SDE_HW_FLUSH_VDC,

					hw_vdc[i]->idx, active);



		SDE_DEBUG_DCE(sde_enc,
@@ -656,9 +658,9 @@ static int _dce_vdc_setup(struct sde_encoder_virt *sde_enc, 
						&cfg,

						!disable_merge_3d);



			if (hw_ctl->ops.update_bitmask_merge3d)

				hw_ctl->ops.update_bitmask_merge3d(

						hw_ctl,

			if (hw_ctl->ops.update_bitmask)

				hw_ctl->ops.update_bitmask(

						hw_ctl, SDE_HW_FLUSH_MERGE_3D,

						hw_pp[i]->merge_3d->idx, true);



			SDE_DEBUG("mode_3d %s, on CTL_%d PP-%d merge3d:%d\n",
@@ -815,8 +817,9 @@ static void _dce_helper_flush_dsc(struct sde_encoder_virt *sde_enc) 


	for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {

		dsc_idx = sde_enc->dirty_dsc_ids[i];

		if (dsc_idx && hw_ctl && hw_ctl->ops.update_bitmask_dsc)

			hw_ctl->ops.update_bitmask_dsc(hw_ctl, dsc_idx, 1);

		if (dsc_idx && hw_ctl && hw_ctl->ops.update_bitmask)

			hw_ctl->ops.update_bitmask(hw_ctl, SDE_HW_FLUSH_DSC,

					dsc_idx, 1);



		sde_enc->dirty_dsc_ids[i] = DSC_NONE;

	}
@@ -833,8 +836,9 @@ void _dce_helper_flush_vdc(struct sde_encoder_virt *sde_enc) 


	for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {

		vdc_idx = sde_enc->dirty_vdc_ids[i];

		if (vdc_idx && hw_ctl && hw_ctl->ops.update_bitmask_vdc)

			hw_ctl->ops.update_bitmask_vdc(hw_ctl, vdc_idx, 1);

		if (vdc_idx && hw_ctl && hw_ctl->ops.update_bitmask)

			hw_ctl->ops.update_bitmask(hw_ctl, SDE_HW_FLUSH_VDC,

					vdc_idx, 1);



		sde_enc->dirty_vdc_ids[i] = VDC_NONE;

	}

msm/sde/sde_encoder_phys_cmd.c

+4 −6
Original line number Diff line number Diff line
@@ -126,17 +126,15 @@ static void _sde_encoder_phys_cmd_update_flush_mask( 
	if (!ctl)

		return;



	if (!ctl->ops.update_bitmask_intf ||

		(test_bit(SDE_CTL_ACTIVE_CFG, &ctl->caps->features) &&

		!ctl->ops.update_bitmask_merge3d)) {

	if (!ctl->ops.update_bitmask) {

		SDE_ERROR("invalid hw_ctl ops %d\n", ctl->idx);

		return;

	}



	ctl->ops.update_bitmask_intf(ctl, phys_enc->intf_idx, 1);

	ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_INTF, phys_enc->intf_idx, 1);



	if (ctl->ops.update_bitmask_merge3d && phys_enc->hw_pp->merge_3d)

		ctl->ops.update_bitmask_merge3d(ctl,

	if (phys_enc->hw_pp->merge_3d)

		ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_MERGE_3D,

			phys_enc->hw_pp->merge_3d->idx, 1);



	SDE_DEBUG_CMDENC(cmd_enc, "update pending flush ctl %d intf_idx %x\n",

msm/sde/sde_encoder_phys_vid.c

+6 −8
Original line number Diff line number Diff line
@@ -760,9 +760,7 @@ static void sde_encoder_phys_vid_enable(struct sde_encoder_phys *phys_enc) 
				!phys_enc->hw_intf, !phys_enc->hw_ctl);

		return;

	}

	if (!ctl->ops.update_bitmask_intf ||

		(test_bit(SDE_CTL_ACTIVE_CFG, &ctl->caps->features) &&

		!ctl->ops.update_bitmask_merge3d)) {

	if (!ctl->ops.update_bitmask) {

		SDE_ERROR("invalid hw_ctl ops %d\n", ctl->idx);

		return;

	}
@@ -800,16 +798,16 @@ static void sde_encoder_phys_vid_enable(struct sde_encoder_phys *phys_enc) 
		goto skip_flush;

	}



	ctl->ops.update_bitmask_intf(ctl, intf->idx, 1);

	ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_INTF, intf->idx, 1);



	if (ctl->ops.update_bitmask_merge3d && phys_enc->hw_pp->merge_3d)

		ctl->ops.update_bitmask_merge3d(ctl,

	if (phys_enc->hw_pp->merge_3d)

		ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_MERGE_3D,

			phys_enc->hw_pp->merge_3d->idx, 1);



	if (phys_enc->hw_intf->cap->type == INTF_DP &&

		phys_enc->comp_type == MSM_DISPLAY_COMPRESSION_DSC &&

		phys_enc->comp_ratio && ctl->ops.update_bitmask_periph)

		ctl->ops.update_bitmask_periph(ctl, intf->idx, 1);

		phys_enc->comp_ratio)

		ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_PERIPH, intf->idx, 1);



skip_flush:

	SDE_DEBUG_VIDENC(vid_enc, "update pending flush ctl %d intf %d\n",

msm/sde/sde_encoder_phys_wb.c

+20 −15
Original line number Diff line number Diff line
@@ -866,11 +866,13 @@ static void _sde_encoder_phys_wb_update_cwb_flush( 
		return;

	}



	if (hw_ctl->ops.update_bitmask_wb)

		hw_ctl->ops.update_bitmask_wb(hw_ctl, hw_wb->idx, 1);

	if (hw_ctl->ops.update_bitmask)

		hw_ctl->ops.update_bitmask(hw_ctl, SDE_HW_FLUSH_WB,

				hw_wb->idx, 1);



	if (hw_ctl->ops.update_bitmask_cdm && hw_cdm)

		hw_ctl->ops.update_bitmask_cdm(hw_ctl, hw_cdm->idx, 1);

	if (hw_ctl->ops.update_bitmask && hw_cdm)

		hw_ctl->ops.update_bitmask(hw_ctl, SDE_HW_FLUSH_CDM,

				hw_cdm->idx, 1);



	if (test_bit(SDE_WB_CWB_CTRL, &hw_wb->caps->features)) {

		for (i = 0; i < crtc->num_mixers; i++) {
@@ -881,14 +883,15 @@ static void _sde_encoder_phys_wb_update_cwb_flush( 
				hw_wb->ops.program_cwb_ctrl(hw_wb, cwb_idx,

						src_pp_idx, dspp_out, enable);



			if (hw_ctl->ops.update_bitmask_cwb)

				hw_ctl->ops.update_bitmask_cwb(hw_ctl,

						cwb_idx, 1);

			if (hw_ctl->ops.update_bitmask)

				hw_ctl->ops.update_bitmask(hw_ctl,

						SDE_HW_FLUSH_CWB, cwb_idx, 1);

		}



		if (need_merge && hw_ctl->ops.update_bitmask_merge3d

		if (need_merge && hw_ctl->ops.update_bitmask

				&& hw_pp && hw_pp->merge_3d)

			hw_ctl->ops.update_bitmask_merge3d(hw_ctl,

			hw_ctl->ops.update_bitmask(hw_ctl,

					SDE_HW_FLUSH_MERGE_3D,

					hw_pp->merge_3d->idx, 1);

	} else {

		phys_enc->hw_mdptop->ops.set_cwb_ppb_cntl(phys_enc->hw_mdptop,
@@ -930,14 +933,16 @@ static void _sde_encoder_phys_wb_update_flush(struct sde_encoder_phys *phys_enc) 
		return;

	}



	if (hw_ctl->ops.update_bitmask_wb)

		hw_ctl->ops.update_bitmask_wb(hw_ctl, hw_wb->idx, 1);

	if (hw_ctl->ops.update_bitmask)

		hw_ctl->ops.update_bitmask(hw_ctl, SDE_HW_FLUSH_WB,

				hw_wb->idx, 1);



	if (hw_ctl->ops.update_bitmask_cdm && hw_cdm)

		hw_ctl->ops.update_bitmask_cdm(hw_ctl, hw_cdm->idx, 1);

	if (hw_ctl->ops.update_bitmask && hw_cdm)

		hw_ctl->ops.update_bitmask(hw_ctl, SDE_HW_FLUSH_CDM,

				hw_cdm->idx, 1);



	if (hw_ctl->ops.update_bitmask_merge3d && hw_pp && hw_pp->merge_3d)

		hw_ctl->ops.update_bitmask_merge3d(hw_ctl,

	if (hw_ctl->ops.update_bitmask && hw_pp && hw_pp->merge_3d)

		hw_ctl->ops.update_bitmask(hw_ctl, SDE_HW_FLUSH_MERGE_3D,

				hw_pp->merge_3d->idx, 1);



	if (hw_ctl->ops.get_pending_flush)