Merge "ARM: dts: msm: Add clock controllers and gdsc nodes for SM6150" (f5061fbb) · Commits · e / devices / android_kernel_fairphone_FP5

qcom/sa6155.dtsi

+28 −0

Original line number	Diff line number	Diff line
		@@ -7,3 +7,31 @@
		qcom,msm-name = "SA6155";
		qcom,msm-id = <384 0x10000>;
		};

		&gcc {
		compatible = "qcom,sa6155-gcc", "syscon";
		/delete-property/ protected-clocks;
		};

		&camcc {
		compatible = "qcom,sa6155-camcc", "syscon";
		vdd_mx-supply = <&VDD_CX_LEVEL>;
		};

		&dispcc {
		compatible = "qcom,sa6155-dispcc", "syscon";
		};

		&gpucc {
		compatible = "qcom,sa6155-gpucc", "syscon";
		vdd_mx-supply = <&VDD_CX_LEVEL>;
		};

		&scc {
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		status = "ok";
		};

		&videocc {
		compatible = "qcom,sa6155-videocc", "syscon";
		};

qcom/sa6155p.dtsi

+28 −0

Original line number	Diff line number	Diff line
		@@ -19,3 +19,31 @@
		/delete-node/ rpmh-regulator-ldoc18;
		/delete-node/ bt_wcn3990;
		};

		&gcc {
		compatible = "qcom,sa6155-gcc", "syscon";
		/delete-property/ protected-clocks;
		};

		&camcc {
		compatible = "qcom,sa6155-camcc", "syscon";
		vdd_mx-supply = <&VDD_CX_LEVEL>;
		};

		&dispcc {
		compatible = "qcom,sa6155-dispcc", "syscon";
		};

		&gpucc {
		compatible = "qcom,sa6155-gpucc", "syscon";
		vdd_mx-supply = <&VDD_CX_LEVEL>;
		};

		&scc {
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		status = "ok";
		};

		&videocc {
		compatible = "qcom,sa6155-videocc", "syscon";
		};

qcom/sm6150-gdsc.dtsi

0 → 100644

+186 −0

Original line number	Diff line number	Diff line
		&soc {
		/* GDSCs in Global CC */
		emac_gdsc: qcom,gdsc@106004 {
		compatible = "qcom,gdsc";
		reg = <0x106004 0x4>;
		regulator-name = "emac_gdsc";
		status = "disabled";
		};

		pcie_0_gdsc: qcom,gdsc@16b004 {
		compatible = "qcom,gdsc";
		reg = <0x16b004 0x4>;
		regulator-name = "pcie_0_gdsc";
		status = "disabled";
		};

		ufs_phy_gdsc: qcom,gdsc@177004 {
		compatible = "qcom,gdsc";
		reg = <0x177004 0x4>;
		regulator-name = "ufs_phy_gdsc";
		status = "disabled";
		};

		usb20_sec_gdsc: qcom,gdsc@1a6004 {
		compatible = "qcom,gdsc";
		reg = <0x1a6004 0x4>;
		regulator-name = "usb20_sec_gdsc";
		status = "disabled";
		};

		usb30_prim_gdsc: qcom,gdsc@10f004 {
		compatible = "qcom,gdsc";
		reg = <0x10f004 0x4>;
		regulator-name = "usb30_prim_gdsc";
		status = "disabled";
		};

		hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc: qcom,gdsc@17d040 {
		compatible = "qcom,gdsc";
		reg = <0x17d040 0x4>;
		regulator-name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc";
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		status = "disabled";
		};

		hlos1_vote_aggre_noc_mmu_tbu1_gdsc: qcom,gdsc@17d044 {
		compatible = "qcom,gdsc";
		reg = <0x17d044 0x4>;
		regulator-name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc";
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		status = "disabled";
		};

		hlos1_vote_aggre_noc_mmu_tbu2_gdsc: qcom,gdsc@17d048 {
		compatible = "qcom,gdsc";
		reg = <0x17d048 0x4>;
		regulator-name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc";
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		status = "disabled";
		};

		hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc: qcom,gdsc@17d04c {
		compatible = "qcom,gdsc";
		reg = <0x17d04c 0x4>;
		regulator-name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc";
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		status = "disabled";
		};

		hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 {
		compatible = "qcom,gdsc";
		reg = <0x17d050 0x4>;
		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		status = "disabled";
		};

		hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@17d054 {
		compatible = "qcom,gdsc";
		reg = <0x17d054 0x4>;
		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc";
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		status = "disabled";
		};

		hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 {
		compatible = "qcom,gdsc";
		reg = <0x17d058 0x4>;
		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		status = "disabled";
		};

		/* GDSCs in Camera CC */
		bps_gdsc: qcom,gdsc@ad06004 {
		compatible = "qcom,gdsc";
		reg = <0xad06004 0x4>;
		regulator-name = "bps_gdsc";
		status = "disabled";
		};

		ife_0_gdsc: qcom,gdsc@ad09004 {
		compatible = "qcom,gdsc";
		reg = <0xad09004 0x4>;
		regulator-name = "ife_0_gdsc";
		status = "disabled";
		};

		ife_1_gdsc: qcom,gdsc@ad0a004 {
		compatible = "qcom,gdsc";
		reg = <0xad0a004 0x4>;
		regulator-name = "ife_1_gdsc";
		status = "disabled";
		};

		ipe_0_gdsc: qcom,gdsc@ad07004 {
		compatible = "qcom,gdsc";
		reg = <0xad07004 0x4>;
		regulator-name = "ipe_0_gdsc";
		status = "disabled";
		};

		titan_top_gdsc: qcom,gdsc@ad0b134 {
		compatible = "qcom,gdsc";
		reg = <0xad0b134 0x4>;
		regulator-name = "titan_top_gdsc";
		status = "disabled";
		};

		/* GDSCs in Display CC */
		mdss_core_gdsc: qcom,gdsc@af03000 {
		compatible = "qcom,gdsc";
		reg = <0xaf03000 0x4>;
		regulator-name = "mdss_core_gdsc";
		qcom,support-hw-trigger;
		status = "disabled";
		proxy-supply = <&mdss_core_gdsc>;
		qcom,proxy-consumer-enable;
		};

		/* GDSCs in Graphics CC */
		gpu_cx_hw_ctrl: syscon@5091540 {
		compatible = "syscon";
		reg = <0x5091540 0x4>;
		};

		gpu_cx_gdsc: qcom,gdsc@509106c {
		compatible = "qcom,gdsc";
		reg = <0x509106c 0x4>;
		regulator-name = "gpu_cx_gdsc";
		hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		qcom,clk-dis-wait-val = <8>;
		status = "disabled";
		};

		gpu_gx_gdsc: qcom,gdsc@509100c {
		compatible = "qcom,gdsc";
		reg = <0x509100c 0x4>;
		regulator-name = "gpu_gx_gdsc";
		status = "disabled";
		};

		/* GDSCs in Video CC */
		vcodec0_gdsc: qcom,gdsc@ab00874 {
		compatible = "qcom,gdsc";
		reg = <0xab00874 0x4>;
		regulator-name = "vcodec0_gdsc";
		status = "disabled";
		};

		venus_gdsc: qcom,gdsc@ab00814 {
		compatible = "qcom,gdsc";
		reg = <0xab00814 0x4>;
		regulator-name = "venus_gdsc";
		status = "disabled";
		};
		};

qcom/sm6150.dtsi

+245 −0

Original line number	Diff line number	Diff line
		#include <dt-bindings/interrupt-controller/arm-gic.h>
		#include <dt-bindings/clock/qcom,rpmh.h>
		#include <dt-bindings/clock/qcom,camcc-sm6150.h>
		#include <dt-bindings/clock/qcom,dispcc-sm6150.h>
		#include <dt-bindings/clock/qcom,gpucc-sm6150.h>
		#include <dt-bindings/clock/qcom,gcc-sm6150.h>
		#include <dt-bindings/clock/qcom,scc-sm6150.h>
		#include <dt-bindings/clock/qcom,videocc-sm6150.h>
		#include <dt-bindings/soc/qcom,rpmh-rsc.h>

		/ {
		@@ -615,6 +621,38 @@
		interrupt-controller;
		};

		clocks {
		xo_board: xo_board {
		compatible = "fixed-clock";
		clock-frequency = <38400000>;
		clock-output-names = "xo_board";
		#clock-cells = <0>;
		};

		sleep_clk: sleep_clk {
		compatible = "fixed-clock";
		clock-frequency = <32000>;
		clock-output-names = "sleep_clk";
		#clock-cells = <0>;
		};

		scc_pll: scc_pll {
		compatible = "fixed-clock";
		clock-frequency = <600000000>;
		clock-output-names = "scc_pll";
		#clock-cells = <0>;
		};

		scc_pll_out_aux: scc_pll_out_aux {
		compatible = "fixed-factor-clock";
		clock-output-names = "scc_pll_out_aux";
		clocks = <&scc_pll>;
		clock-mult = <1>;
		clock-div = <2>;
		#clock-cells = <0>;
		};
		};

		qcom,msm-imem@146aa000 {
		compatible = "qcom,msm-imem";
		reg = <0x146aa000 0x1000>;
		@@ -714,9 +752,216 @@
		<ACTIVE_TCS 2>,
		<CONTROL_TCS 0>;
		};

		gcc: clock-controller@100000 {
		compatible = "qcom,sm6150-gcc", "syscon";
		reg = <0x100000 0x1f0000>;
		reg-name = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
		vdd_mx-supply = <&VDD_MX_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
		<&rpmhcc RPMH_CXO_CLK_A>,
		<&sleep_clk>;
		clock-names = "bi_tcxo",
		"bi_tcxo_ao",
		"sleep_clk";
		protected-clocks = <GCC_SDR_CORE_CLK>,
		<GCC_SDR_WR0_MEM_CLK>,
		<GCC_SDR_WR1_MEM_CLK>,
		<GCC_SDR_WR2_MEM_CLK>,
		<GCC_SDR_CSR_HCLK>,
		<GCC_SDR_PRI_MI2S_CLK>,
		<GCC_SDR_SEC_MI2S_CLK>;
		#clock-cells = <1>;
		#reset-cells = <1>;
		};

		camcc: clock-controller@ad00000 {
		compatible = "qcom,sm6150-camcc", "syscon";
		reg = <0xad00000 0x10000>;
		reg-name = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		vdd_mx-supply = <&VDD_MX_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "bi_tcxo";
		#clock-cells = <1>;
		#reset-cells = <1>;
		};

		dispcc: clock-controller@af00000 {
		compatible = "qcom,sm6150-dispcc", "syscon";
		reg = <0xaf00000 0x20000>;
		reg-name = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
		<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
		clock-names = "bi_tcxo", "gpll0";
		#clock-cells = <1>;
		#reset-cells = <1>;
		};

		gpucc: clock-controller@5090000 {
		compatible = "qcom,sm6150-gpucc", "syscon";
		reg = <0x5090000 0x9000>;
		reg-name = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		vdd_mx-supply = <&VDD_MX_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
		clock-names = "bi_tcxo", "gpll0";
		#clock-cells = <1>;
		#reset-cells = <1>;
		};

		scc: clock-controller@62b10000 {
		compatible = "qcom,sa6155-scc", "syscon";
		reg = <0x62b10000 0x30000>;
		reg-name = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
		<&sleep_clk>, <&scc_pll>,
		<&scc_pll_out_aux>;
		clock-names = "bi_tcxo", "sleep_clk",
		"scc_pll", "scc_pll_out_aux";
		#clock-cells = <1>;
		#reset-cells = <1>;
		status = "disabled";
		};

		videocc: clock-controller@ab00000 {
		compatible = "qcom,sm6150-videocc", "syscon";
		reg = <0xab00000 0x10000>;
		reg-name = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
		clock-names = "bi_tcxo", "sleep_clk";
		#clock-cells = <1>;
		#reset-cells = <1>;
		};

		apsscc: syscon@182a0000 {
		compatible = "syscon";
		reg = <0x182a0000 0x1c>;
		};

		mccc: syscon@90b0000 {
		compatible = "syscon";
		reg = <0x90b0000 0x54>;
		};

		debugcc: debug-clock-controller@0 {
		compatible = "qcom,sm6150-debugcc";
		qcom,apsscc = <&apsscc>;
		qcom,camcc = <&camcc>;
		qcom,dispcc = <&dispcc>;
		qcom,gcc = <&gcc>;
		qcom,gpucc = <&gpucc>;
		qcom,mccc = <&mccc>;
		qcom,videocc = <&videocc>;
		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "xo_clk_src";
		#clock-cells = <1>;
		};
		};

		#include "sm6150-qupv3.dtsi"
		#include "sm6150-pinctrl.dtsi"
		#include "sm6150-pm.dtsi"
		#include "sm6150-regulator.dtsi"
		#include "sm6150-gdsc.dtsi"

		&emac_gdsc {
		status = "ok";
		};

		&pcie_0_gdsc {
		status = "ok";
		};

		&ufs_phy_gdsc {
		status = "ok";
		};

		&usb30_prim_gdsc {
		status = "ok";
		};

		&usb20_sec_gdsc {
		status = "ok";
		};

		&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc {
		status = "ok";
		};

		&hlos1_vote_aggre_noc_mmu_tbu1_gdsc {
		status = "ok";
		};

		&hlos1_vote_aggre_noc_mmu_tbu2_gdsc {
		status = "ok";
		};

		&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc {
		status = "ok";
		};

		&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
		status = "ok";
		};

		&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc {
		status = "ok";
		};

		&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
		status = "ok";
		};

		&bps_gdsc {
		qcom,support-hw-trigger;
		status = "ok";
		};

		&ife_0_gdsc {
		status = "ok";
		};

		&ife_1_gdsc {
		status = "ok";
		};

		&ipe_0_gdsc {
		qcom,support-hw-trigger;
		status = "ok";
		};

		&titan_top_gdsc {
		status = "ok";
		};

		&mdss_core_gdsc {
		status = "ok";
		};

		&gpu_cx_gdsc {
		parent-supply = <&VDD_CX_LEVEL>;
		status = "ok";
		};

		&gpu_gx_gdsc {
		clock-names = "core_root_clk";
		clocks = <&gpucc GPU_CC_GX_GFX3D_CLK_SRC>;
		qcom,force-enable-root-clk;
		parent-supply = <&VDD_CX_LEVEL>;
		status = "ok";
		};

		&vcodec0_gdsc {
		qcom,support-hw-trigger;
		status = "ok";
		};

		&venus_gdsc {
		status = "ok";
		};