Loading qcom/yupik-rumi.dtsi +4 −0 Original line number Diff line number Diff line Loading @@ -178,3 +178,7 @@ &videocc { clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>, <&gcc GCC_VIDEO_AHB_CLK>; }; &camcc { clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>, <&gcc GCC_CAMERA_AHB_CLK>; }; qcom/yupik.dtsi +8 −2 Original line number Diff line number Diff line Loading @@ -635,8 +635,14 @@ }; camcc: clock-controller@ad00000 { compatible = "qcom,dummycc"; clock-output-names = "camcc_clocks"; compatible = "qcom,yupik-camcc", "syscon"; reg = <0xad00000 0x10000>; reg-names = "cc_base"; vdd_mx-supply = <&VDD_MX_LEVEL>; vdd_cx-supply = <&VDD_CX_LEVEL>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, <&gcc GCC_CAMERA_AHB_CLK>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "cfg_ahb"; #clock-cells = <1>; #reset-cells = <1>; }; Loading Loading
qcom/yupik-rumi.dtsi +4 −0 Original line number Diff line number Diff line Loading @@ -178,3 +178,7 @@ &videocc { clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>, <&gcc GCC_VIDEO_AHB_CLK>; }; &camcc { clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>, <&gcc GCC_CAMERA_AHB_CLK>; };
qcom/yupik.dtsi +8 −2 Original line number Diff line number Diff line Loading @@ -635,8 +635,14 @@ }; camcc: clock-controller@ad00000 { compatible = "qcom,dummycc"; clock-output-names = "camcc_clocks"; compatible = "qcom,yupik-camcc", "syscon"; reg = <0xad00000 0x10000>; reg-names = "cc_base"; vdd_mx-supply = <&VDD_MX_LEVEL>; vdd_cx-supply = <&VDD_CX_LEVEL>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, <&gcc GCC_CAMERA_AHB_CLK>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "cfg_ahb"; #clock-cells = <1>; #reset-cells = <1>; }; Loading