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Commit f4bc54b5 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-5.1' of git://people.freedesktop.org/~agd5f/linux into drm-next 



Updates for 5.1:
- GDS fixes
- Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES interface
- GPUVM fixes
- PCIE DPM switching fixes for vega20
- Vega10 uclk DPM regression fix
- DC Freesync fixes
- DC ABM fixes
- Various DC cleanups

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190208210214.27666-1-alexander.deucher@amd.com
parents 5ea3998d 04612213

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+12 −1
Original line number Diff line number Diff line
@@ -214,6 +214,7 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs 
		case AMDGPU_CHUNK_ID_DEPENDENCIES:

		case AMDGPU_CHUNK_ID_SYNCOBJ_IN:

		case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:

		case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:

			break;



		default:
@@ -1090,6 +1091,15 @@ static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p, 


		fence = amdgpu_ctx_get_fence(ctx, entity,

					     deps[i].handle);



		if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {

			struct drm_sched_fence *s_fence = to_drm_sched_fence(fence);

			struct dma_fence *old = fence;



			fence = dma_fence_get(&s_fence->scheduled);

			dma_fence_put(old);

		}



		if (IS_ERR(fence)) {

			r = PTR_ERR(fence);

			amdgpu_ctx_put(ctx);
@@ -1177,7 +1187,8 @@ static int amdgpu_cs_dependencies(struct amdgpu_device *adev, 


		chunk = &p->chunks[i];



		if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES) {

		if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES ||

		    chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {

			r = amdgpu_cs_process_fence_dep(p, chunk);

			if (r)

				return r;

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+46 −12
Original line number Diff line number Diff line
@@ -3618,6 +3618,38 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 
	return r;

}



static void amdgpu_device_get_min_pci_speed_width(struct amdgpu_device *adev,

						  enum pci_bus_speed *speed,

						  enum pcie_link_width *width)

{

	struct pci_dev *pdev = adev->pdev;

	enum pci_bus_speed cur_speed;

	enum pcie_link_width cur_width;



	*speed = PCI_SPEED_UNKNOWN;

	*width = PCIE_LNK_WIDTH_UNKNOWN;



	while (pdev) {

		cur_speed = pcie_get_speed_cap(pdev);

		cur_width = pcie_get_width_cap(pdev);



		if (cur_speed != PCI_SPEED_UNKNOWN) {

			if (*speed == PCI_SPEED_UNKNOWN)

				*speed = cur_speed;

			else if (cur_speed < *speed)

				*speed = cur_speed;

		}



		if (cur_width != PCIE_LNK_WIDTH_UNKNOWN) {

			if (*width == PCIE_LNK_WIDTH_UNKNOWN)

				*width = cur_width;

			else if (cur_width < *width)

				*width = cur_width;

		}

		pdev = pci_upstream_bridge(pdev);

	}

}



/**

 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot

 *
@@ -3630,8 +3662,8 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 
static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)

{

	struct pci_dev *pdev;

	enum pci_bus_speed speed_cap;

	enum pcie_link_width link_width;

	enum pci_bus_speed speed_cap, platform_speed_cap;

	enum pcie_link_width platform_link_width;



	if (amdgpu_pcie_gen_cap)

		adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
@@ -3648,6 +3680,12 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) 
		return;

	}



	if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)

		return;



	amdgpu_device_get_min_pci_speed_width(adev, &platform_speed_cap,

					      &platform_link_width);



	if (adev->pm.pcie_gen_mask == 0) {

		/* asic caps */

		pdev = adev->pdev;
@@ -3673,22 +3711,20 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) 
				adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;

		}

		/* platform caps */

		pdev = adev->ddev->pdev->bus->self;

		speed_cap = pcie_get_speed_cap(pdev);

		if (speed_cap == PCI_SPEED_UNKNOWN) {

		if (platform_speed_cap == PCI_SPEED_UNKNOWN) {

			adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |

						   CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);

		} else {

			if (speed_cap == PCIE_SPEED_16_0GT)

			if (platform_speed_cap == PCIE_SPEED_16_0GT)

				adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |

							   CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |

							   CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |

							   CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);

			else if (speed_cap == PCIE_SPEED_8_0GT)

			else if (platform_speed_cap == PCIE_SPEED_8_0GT)

				adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |

							   CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |

							   CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);

			else if (speed_cap == PCIE_SPEED_5_0GT)

			else if (platform_speed_cap == PCIE_SPEED_5_0GT)

				adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |

							   CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);

			else
@@ -3697,12 +3733,10 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) 
		}

	}

	if (adev->pm.pcie_mlw_mask == 0) {

		pdev = adev->ddev->pdev->bus->self;

		link_width = pcie_get_width_cap(pdev);

		if (link_width == PCIE_LNK_WIDTH_UNKNOWN) {

		if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {

			adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;

		} else {

			switch (link_width) {

			switch (platform_link_width) {

			case PCIE_LNK_X32:

				adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |

							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+3 −1
Original line number Diff line number Diff line
@@ -71,9 +71,11 @@ 
 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).

 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.

 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation.

 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES

 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID

 */

#define KMS_DRIVER_MAJOR	3

#define KMS_DRIVER_MINOR	27

#define KMS_DRIVER_MINOR	29

#define KMS_DRIVER_PATCHLEVEL	0



int amdgpu_vram_limit = 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h

+2 −0
Original line number Diff line number Diff line
@@ -37,6 +37,8 @@ struct amdgpu_gds { 
	struct amdgpu_gds_asic_info	mem;

	struct amdgpu_gds_asic_info	gws;

	struct amdgpu_gds_asic_info	oa;

	uint32_t			gds_compute_max_wave_id;



	/* At present, GDS, GWS and OA resources for gfx (graphics)

	 * is always pre-allocated and available for graphics operation.

	 * Such resource is shared between all gfx clients.

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

+0 −7
Original line number Diff line number Diff line
@@ -54,10 +54,6 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 


	memset(&bp, 0, sizeof(bp));

	*obj = NULL;

	/* At least align on page size */

	if (alignment < PAGE_SIZE) {

		alignment = PAGE_SIZE;

	}



	bp.size = size;

	bp.byte_align = alignment;
@@ -244,9 +240,6 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 
			return -EINVAL;

		}

		flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;

		/* GDS allocations must be DW aligned */

		if (args->in.domains & AMDGPU_GEM_DOMAIN_GDS)

			size = ALIGN(size, 4);

	}



	if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {